Subprograms Subprograms Similar to subprograms found in other

Subprograms

Subprograms ä Similar to subprograms found in other languages ä Allow repeatedly used code to be referenced multiple times without rewriting ä Break down large blocks of code into small, more manageable parts ä VHDL provides functions and procedures

Subprograms (cont’d) ä Contain sequential statements similar to processes ä May declare local variables, constants ä Executed when called from a sequential statement. ä Local Variables are re-initialized every time a subprogram is called. ä Parameters of calling routine are known as actuals, while the parameters of the declared subprogram are known as formals. ä Up level referencing to higher level variables and signals is allowed. ä Recursive calls by functions and procedures are allowed ä Attributes of signals cannot be accessed within subprograms

Functions ä ä Produce a single return value Called by expressions Cannot modify the parameters passed to them Require a RETURN statement FUNCTION add_bits (a, b : IN BIT) RETURN BIT IS BEGIN -- functions cannot return multiple values RETURN (a XOR b); END add_bits; FUNCTION add_bits 2 (a, b : IN BIT) RETURN BIT IS VARIABLE result : BIT; -- variable is local to function BEGIN result : = (a XOR b); RETURN result; -- the two functions are equivalent END add_bits 2;

Functions x

Functions

Functions

Functions

Functions

Example of a Function

Example of a Function (cont)

Functions ARCHITECTURE behavior OF adder IS BEGIN PROCESS (enable, x, y) BEGIN IF (enable = '1') THEN result <= add_bits(x, y); carry <= x AND y; ELSE carry, result <= '0'; END PROCESS; END behavior; ä ä FUNCTION add_bits (a, b : IN BIT) Functions must be called by other statements Parameters use positional association

Procedures

Procedures (cont)

Procedures (cont)

Example of a Procedure

Another Example of a Procedure

Summary on Sequential Statements

Procedures ä May produce multiple output values ä Are invoked by statements ä May modify the parameters PROCEDURE add_bits 3 (SIGNAL a, b, en : IN BIT; SIGNAL temp_result, temp_carry : OUT BIT) IS BEGIN -- procedures can return multiple values temp_result <= (a XOR b) AND en; temp_carry <= a AND b AND en; END add_bits 3; l Do not require a RETURN statement

Procedures (Cont. ) ARCHITECTURE behavior OF adder IS BEGIN PROCESS (enable, x, y) BEGIN add_bits 3(x, y, enable, result, carry); END PROCESS; END behavior; l The parameters must be compatible in terms of data flow and data type ä With parameter passing, it is possible to further simplify the architecture PROCEDURE add_bits 3 (SIGNAL a, b, en : IN BIT; SIGNAL temp_result, temp_carry : OUT BIT)

Signal Resolution and Buses Execution phase Signal update phase Transaction queue OR Bus Resolution Function AND Resolved signal

Bus Resolution Smoke Generator ä VHDL does not allow multiple concurrent signal assignments to the same signal äLIBRARY Multiple sequential signal assignments are attlib; USE attlib. att_mvl. ALL; -- this code will generate an error allowed ENTITY bus IS PORT (a, b, c : IN MVL; z : OUT MVL); END bus; ARCHITECTURE smoke_generator OF bus IS SIGNAL circuit_node : MVL; BEGIN circuit_node <= a; circuit_node <= b; circuit_node <= c; z <= circuit_node; END smoke_generator;

Bus Resolution Functions ä Are used to determine the assigned value when there are multiple signal drivers to the FUNCTION wired_and (drivers : MVL_VECTOR) RETURN MVL IS same signal VARIABLE accumulate : MVL : = '1'; BEGIN FOR i IN drivers'RANGE LOOP accumulate : = accumulate AND drivers(i); END LOOP; RETURN accumulate; END wired_and; l Bus resolution functions may be user defined or called from a package

Bus Resolution Smoke Generator Fixed ä A signal which has a bus resolution function associated with it may have LIBRARY attlib; USE attlib. att_mvl. ALL; multiple drivers USE WORK. bus_resolution. ALL; ENTITY bus IS PORT (a, b, c : IN MVL; z : OUT MVL); END bus; ARCHITECTURE fixed OF bus IS SIGNAL circuit_node : wired_and MVL; BEGIN circuit_node <= a; circuit_node <= b; circuit_node <= c; z <= circuit_node; END fixed;

Null Transactions ä How can a driver be disconnected (i. e. not influence the output at all)? ä ä Use the null waveform element Example bus_out <= NULL AFTER 17 ns; ä What happens if all drivers of a resolved signal are disconnected? ä ä ä Use register kind in signal declaration to keep most recently determined value Use bus kind in signal declaration if resolution function will determine the value Example signal t : wired_bus BUS; signal u : BIT REGISTER;

Concurrent Statement ä Exists outside of a process but in an architecture ä The process is itself a concurrent statement all processes scheduled to run concurrently ä Concurrent signal assignment is a short hand form for a single statement process -- equivalent to process containing one statement, sensitive to changes on the right hand side. ä Used frequently in DATAFLOW style descriptions

The Process

Concurrent Signal Assignment

Concurrent Assignment Statements

Concurrent Signal Sensitivity ä Concurrent Statements are sensitive to all signals on the input side ä If a signal appears on both sides, the statement is sensitive to changes in its own output. ä A <= A+B; will be evaluated when B changes. This will change A and the statement will be evaluated again. ä Time will not be able to advance because the statement keeps executing.

Conditional Signal Statement

Example of Conditional Signal Statement

Selected Signal Statement

Example of Selected Signal Assignment

Concurrent Procedure Call ä IN, OUT and INOUT parameter modes ä Allows return of more than 1 value (unlike function call) ä Considered a statement ä Equivalent to a process containing the single procedure call followed by a wait on parameters of mode in or inout

Example of Concurrent Procedure Call

Sequential vs. Concurrent Statement in Simulation Cycle ä ä ä ä VHDL is inherently a concurrent language All VHDL processes execute concurrently Concurrent signal assignment statements are actually oneline processes VHDL statements execute sequentially within a process Concurrent processes with sequential execution within a process offers maximum flexibility Supports various levels of abstraction Supports modeling of concurrent and sequential events as observed in real systems

Blocks

Blocks ä Blocks are concurrent statements and provide a mechanism to partition an architecture description ä Items declared in declarative region of block are visible only inside the block, e. g. : ä signals, subprograms ä Blocks may be nested to define a hierarchical partitioning of the architectural description ä Blocks may contain Guards for disabling drives.

Blocks

Nested Blocks

äEnd of this file

Modeling Styles ä Behavioral Modeling ä Explicit definition of mathematical relationship between the input and output ä No implementation information ä Structural Modeling ä Implicit definition of I/O relationship through particular structure ä Interconnection of components

Behavioral Modeling ä All VHDL processes execute concurrently ä Non-procedural ä Data-flow ä Concurrent execution ä Procedural ä Algorithmic ä Sequential execution of statements ä Equivalent to a single concurrent statement

Data Flow Model ä Concurrent Statements ä Execute in arbitrary order ä Execute only when any of input variables changes Local_Sig_1 <= In_1 AND In_2 ; Local_Sig_2 <= In_1 OR Local_Sig_1;

Signal Assignment Statements ä Two Types ä Conditional concurrent signal assignment statement ä Selected concurrent signal assignment statement ä Each of These Has a Sequential Process Equivalent ä Either Form Can Be Used and Are Equivalent

BIT or BOOLEAN? ä Logical Types Are Not Equal ä BIT for signals ä ‘ 0’ or ‘ 1’ ä Character type ä BOOLEAN for conditions ä TRUE or FALSE

Conditional Concurrent Syntax signal_identifier <= options conditional_waveforms ; options <= [ guarded ] [ delay_mechanisms ] conditional_waveforms <= { waveform when condition else } waveform [ when condition ]

Waveform Syntax waveform <= ( value_expression [ after time_expression ] ) { , . . . }

Operator Precedence ä Highest to Lowest ä Unary operator: NOT ä Relational operators: =, /=, <, <=, >, >= ä Boolean (bitwise): AND, OR, NAND, NOR, XNOR ä Parentheses Can Be Used to ä Force particular order of evaluation ä Improve readability of expressions

Type Declaration/Definition type identifier is type_definition ; type_definition <= scalar_type_definition composite_type_definition access_type_definition file_type_definition | | |

Scalar Type scalar_type_definition <= enumeration_type_definition | integer_type_definition | floating_type_definition | physical_type_definition

Predefined Enumerated Types ä type severity_level is ( note, warning, error, failure ); ä type Boolean is ( false, true ); ä Used to model abstract conditions ä type bit is ( '0', '1' ); ä Used to model hardware logic levels

Bit-Vector Type ä Useful Composite Type Since It Groups Bits Together Which Can Represent Register Contents or Binary Numbers. signal Out_Port_Adx: Bit_Vector ( 15 downto 0 );

Specifying Values with String Literal Out_Port_Adx <= B ” 0110_1001”; Out_Port_Adx <= X ” 69” ; Out_Port_Adx <= O ” 151” ;

HW 2 -11 LIBRARY ieee ; USE ieee. std_logic_1164. all ; PACKAGE Clock_2_11_pkg IS COMPONENT Clock_2_11 --GENERIC ( ) ; PORT ( Clock. Out : out END COMPONENT ; END Clock_2_11_pkg ; bit : = ' 0' ) ;

HW 2 -11 ENTITY Clock_2_11 IS -- GENERIC ( ); PORT ( Clock. Out : out END Clock_2_11 ; bit : = ' 0' );

HW 2 -11 ARCHITECTURE KJH_Clock OF Clock_2_11 IS BEGIN clock_gen : PROCESS BEGIN Clock. Out <= '1'; WAIT FOR 10 ns ; Clockout <= '0'; WAIT FOR 10 ns ; END PROCESS clock_gen ; END KJH_Clock ;

Sources ä Prof. Krzysztof Kuchcinski ä VLSI, Ohio University, Prof. Starzyk ä Professor K. J. Hintz. ä California State University Northridge