SUBJECT COMPUTER ORGANISATION SUBJECT CODE 2140707 B E

SUBJECT: COMPUTER ORGANISATION SUBJECT CODE: 2140707 B. E. 4 th SEMESTER GUIDED BY PROF. BHUMIKA BHATT PROF. MEHUL KHATIWALA

CONTRIBUTORS 1. 2. 3. 4. 5. SNEHA GANGWANI(130420107022) KHUSHBOO GOHEL(130420107023) HARSH GANDHI(130420107024) HIREN CHAUDHRY(130420107025) JAY DHANANI(130420107026)

Central Processing Unit Introduction General register organisation Stack organisation Instruction format Addressing modes Data transfer and manipulation Program control RISC(Reduced Instruction Set Computer)

MAJOR COMPONENTS OF CPU Storage Components Registers Flags Execution (Processing) Components Arithmetic Logic Unit(ALU) Arithmetic calculations, Logical computations, Shifts/Rotates Transfer Components Bus Control Components Control Unit Register File ALU Control Unit

REGISTERS In Basic Computer, there is only one general purpose register, the Accumulator (AC) In modern CPUs, there are many general purpose registers It is advantageous to have many registers Transfer between registers within the processor are relatively fast Going “off the processor” to access memory is much slower

GENERAL REGISTER ORGANIZATION BUS: A, B Clock Input (7 lines) R 1 R 2 R 3 R 4 R 5 R 6 R 7 Load (7 lines) SELA { 3 x 8 decoder MUX A bus SELD OPR B bus ALU Output } SELB

OPERATION OF CONTROL UNIT The control unit Directs the information flow through ALU by - Selecting various Components in the system - Selecting the Function of ALU Example: R 1 R 2 + R 3 [1] MUX A selector (SELA): BUS A R 2 [2] MUX B selector (SELB): BUS B R 3 [3] ALU operation selector (OPR): ALU to ADD [4] Decoder destination selector (SELD): R 1 Out Bus Control Word 3 SELA 3 SELB 3 SELD 5 OPR Encoding of register selection fields Binary Code. SELA SELB 000 Input. None 001 R 1 R 1 010 R 2 R 2 011 R 3 R 3 100 R 4 R 4 101 R 5 R 5 110 R 6 R 6 111 R 7 R 7 SELD

ALU CONTROL Encoding of ALU operations OPR Select 000001 000101 00110 01000 01010 01100 01110 10000 11000 Operation Symbol Transfer ATSFA Increment A INCA ADD A + BADD Subtract A - B SUB Decrement A DECA AND A and B AND OR A and B OR XOR A and B XOR Complement A COMA Shift right A SHRA Shift left ASHLA Examples of ALU Microoperations Symbolic Designation Microoperation SELA SELB SELD OPR Control Word R 1 R 2 R 3 R 2 R 3 R 1 SUB 010 011 00101 R 4 R 5 R 4 OR 100 101 100 01010 R 6 + 1 R 6 - R 6 INCA 110 00001 R 7 R 1 - R 7 TSFA 001 000 111 00000 Output R 2 - None TSFA 010 000 00000 Input - None TSFA 000 00000 R 4 shl R 4 - R 4 SHLA 100 000 11000 R 5 R 5 XOR 101 101 01100 Output Input

REGISTER STACK ORGANIZATION Stack - Very useful feature for nested subroutines, nested interrupt services - Also efficient for arithmetic expression evaluation - Storage which can be accessed in LIFO - Pointer: SP OR POS - Only PUSH and POP operations are applicable stack Register Stack 63 Flags FULL EMPTY Stack pointer SP 6 bits Push, Pop operations C B A DR /* Initially, SP = 0, EMPTY = 1, FULL = 0 */ PUSH SP + 1 M[SP] DR If (SP = 0) then (FULL 1) EMPTY 0 Address POP DR M[SP] SP 1 If (SP = 0) then (EMPTY 1) FULL 0 4 3 2 1 0

MEMORY STACK ORGANIZATION 1000 Memory with Program, Data, and Stack Segments PC Program (instructions) AR Data (operands) SP - A portion of memory is used as a stack with a processor register as a stack pointer 3000 stack 3997 3998 3999 4000 4001 Stack grows In this direction - PUSH: SP - 1 M[SP] DR - POP: DR M[SP] SP + 1 - Most computers do not provide hardware to check stack overflow (full stack) or underflow (empty stack) must be done in software

REVERSE POLISH NOTATION • Arithmetic Expressions: A + B A+B +AB AB+ Infix notation Prefix or Polish notation Postfix or reverse Polish notation - The reverse Polish notation is very suitable for stack manipulation • Evaluation of Arithmetic Expressions Any arithmetic expression can be expressed in parenthesis-free Polish notation, including reverse Polish notation (3 * 4) + (5 * 6) 34*56*+ 3 4 3 12 5 12 6 5 12 3 4 * 5 6 30 12 42 * +

Three-Address Instructions • Computers with three-address instruction formats can use each address field to specify either a processor register or a memory operand. • The program in assembly language that evaluates X=(A+B)*(C+D) is shown below, together with comments that explain the register transfer operation of each instruction.

The advantage of three-address is that it results in short programs when evaluation arithmetic expressions. The disadvantage is that the binary-coded instructions require too many bits to specify threeaddress. An example of a commercial computer that uses three-address instruction is the Cyber 170.

Two-Address Instruction • Two-address instructions are the most common in commercial computers. The program to evaluate X=(A+B)*(C+D) is as follows : • The MOV instruction moves or transfers the operands to and from memory and processor registers. The first symbol listed in an instruction is assumed to be both a source and the destination where the result of the operation is transferred.

One-Address Instruction • One-Address Instruction use an implied accumulator (A) register for all data manipulation. For manipulation and division there is a need for a second register. • The program to evaluate X+(A+B)*(C+D) is • ALL operations are done between the AC register and a memory operand. T is the address of a temporary memory location required for storing the intermediate result.

Zero-Address Instruction A tack-organized computer does not use an address field for the instructions ADD and MUL. The PUSH and POP instructions, however, need an address field to specify the operand that communicates with the stack. The following program shows how X=(A+B)*(C+D) will be written for a stack-organized computer.

To evaluate arithmetic expressions in stack computer, it is necessary to convert the expression into reverse Polish notation. The name “zero-address” is given to this type of computer because of the absence of an address field in the computational instructions.

ADDRESSING MODES 1) Implied Mode : In this mode the operands are specified implicitly in the definition of the instruction. For example, the instruction “complement accumulator” is an implied mode instruction because the operand in the accumulator register is implied in the definition of the instruction. 1) Immediate Mode: In this mode the operand is specified in the instruction itself. In other words, an immediate mode instruction has an operand field rather than the address field. Immediate mode instruction are useful for initializing registers to a constant value.

3) Register Mode : In this mode the operands are in registers that reside within the CPU. The particular register is selected from a register field in the instruction. MOV R 1, R 2 4) Register Indirect Mode : In this mode the instruction specifies a register in the CPU whose contents give the address of the operand I in memory. In other words, the selected register contains the address of the operand rather than the operand itself. 5) Autoincrement and Autodecrement Mode: This is similar to the register in direct mode except that the register is incremented or decremented after its value is used to access memory.

6) Direct Address Mode : In this mode the effective address is equal to the address part of the instruction. The operand is resides in the memory and its address is given directly by the address field of the instruction. 7) Indirect Address Mode : In this mode the address field of the instruction gives the address of the effective address is stored in the memory. Control fethes the instruction from memory and uses its address part to access memory again to read the effective address. Effective address= address part of the instruction +content of CPU register.

8) Relative Address Mode: In this mode the content of the program counter is added to the address part of the instruction in order to obtain the effective address 9) Indexed Addressing Mode : In this mode the content of an index register is added to the part of the instruction to obtain the effective address. Index register is the special CPU register that contains an index value. The address field of the instruction defines the beginning address of a data array in the memory. 10) Base Register Addressing Mode: In this mode the content of the base register is added to the address part of the instruction to obtain the effective address. This is similar to the indexed addressing mode except that the register is now called the base register instead of an index register.

Data Transfer instructions Most computer instructions can be classified into three categories: 1) Data transfer 2) Data manipulation 3) Program control instructions

Addressing modes Data Transfer Instructions with Different Addressing Modes Assembly Convention Direct address LD ADR Indirect address LD @ADR Relative address LD $ADR Immediate operand LD #NBR Index addressing LD ADR(X) Register LD R 1 Register indirect LD (R 1) Autoincrement LD (R 1)+ Autodecrement LD -(R 1) Mode Register Transfer AC M[ADR] AC M[M[ADR]] AC M[PC + ADR] AC NBR AC M[ADR + XR] AC R 1 AC M[R 1], R 1 + 1 R 1 - 1, AC M[R 1]

• Typical Data Transfer Instruction: Load : transfer from memory to a processor register, usually an AC (memory read) Store : transfer from a processor register into memory (memory write) Move : transfer from one register to another register Exchange : swap information between two registers or a register and a memory word Input / Output : transfer data among processor registers and input/output device Push/Pop : transfer data between processor registers and a memory stack

Overview Typical Data Transfer Instructions Name Load Store Move Exchange Input Output Push Pop Mnemonic LD ST MOV XCH IN OUT PUSH POP 25

Program control • Program Control Instruction: Branch and Jump instructions are used interchangeably to mean the same thing NAME MNEMONIC BRANCH BR JUMP JMP SKIP SKP CALL RETURN RET COMPARE (BY SUBTRACTION) CMP TEST (BY ENDING) TST

• Status Bit Conditions: Condition Code Bit or Flag Bit The bits are set or cleared as a result of an operation performed in the ALU Shift Instructions Arithmetic Instructions Name Mnemonic Increment INC Decrement DEC Add ADD Subtract SUB Multiply MUL Divide DIV Add with Carry ADDC Subtract with Borrow SUBB Negate(2’s Complement) NEG Logical and Bit Manipulation Logical shift right Logical shift left Arithmetic shift right Arithmetic shift left Rotate right Rotate left Rotate right thru carry Rotate left thru carry Name SHR SHL SHRA SHLA ROR ROL RORC ROLC Mnemonic Clear CLR Complement COM AND Instructions. AND OR OR Exclusive-OR XOR Clear carry CLRC Set carry SETC Complement carry COMC Enable interrupt EI Disable interrupt DI

Subroutine Call and Return CALL: SP<-SP-1 //decrement stack point M[SP]<-PC //push content of pc onto stack PC<-effective address //transfer control to subroutine RETURN: PC<-M[SP]//pop stack &trabsfer to pc SP<-SP+1//increment stack pointer

Typical set of branch instruction MNEMOIC CONDITION EXPLANATION BEQ == Branch if equal BNE != Branch if not equal BGT > Branch if greater than BLT < Branch if less than BGE >= Branch if greater or equal BLE <= Branch if less than or equal BRA Branch always (unconditional)

BHI UNSIGNED > Branch if higher BLO UNSIGNED < Branch if lower BHS UNSIGNED >= Branch if higher or same BLS UNSIGNED <= Branch if lower or same BCS Branch if carry set BCC Branch if carry clear BVS Branch if overflow set BVC Branch if overflow clear BPL >=0 Branch if ‘plus’ BMI <0 Branch if ‘minus’

Program interrupt Transfer program control from a currently running program to another service program as a result of an external or internal generated request Control returns to the original program after the service program is executed.

Interrupt Service Program Subroutine Call An interrupt is initiated by an internal or external signal (except for software interrupt) n A subroutine call is initiated from the execution of an instruction (CALL) The address of the interrupt service program is determined by the hardware n The address of the subroutine call is determined from the address field of an instruction An interrupt procedure stores all the information necessary to define the state of the CPU n A subroutine call stores only the program counter (Return address)

Program Status Word (PSW) The collection of all status bit conditions in the CPU Two CPU Operating Modes Supervisor (System) Mode : Privileged Instruction When the CPU is executing a program that is part of the operating system

Types of Interrupts External Interrupts come from I/O device, from a timing device, from a circuit monitoring the power supply, or from any other external source Internal Interrupts or TRAP caused by register overflow, attempt to divide by zero, an invalid operation code, stack overflow, and protection violation Software Interrupts initiated by executing an instruction (INT or RST) used by the programmer to initiate an interrupt procedure at any desired point in the program

Control Unit A control unit is circuitry that directs operations within a computer's processor. It lets the computer's logic unit, memory, as well as both input and output devices know how to respond to instructions received from a program. Examples of devices that utilize control units include CPUs and GPUs.

• A control unit works by receiving input information that it converts into control signals, which are then sent to the central processor. The computer's processor then tells the attached hardware what operations carry out. The functions a control unit performs depend on the type of CPU, due to the variance of architecture between different manufacturers. The following diagram illustrates how instructions from a program are processed.

Reduced Instruction Set Computer (RISC) Complex Instruction Set Computer (CISC) Major characteristics of a CISC architecture 1) A large number of instructions -typically from 100 to 250 instruction. 2) Some instructions that perform specialized tasks and are used infrequently. 3) A large variety of addressing modes -typically from 5 to 20 different modes. 4) Variable-length instruction formats. 5) Instructions that manipulate operands in memory.

Reduced Instruction Set Computer (RISC) Major characteristics of a RISC architecture 1) Relatively few instructions. 2) Relatively few addressing modes. 3) Memory access limited to load and store instruction. 4) All operations done within the registers of the CPU. 5) Fixed-length, easily decoded instruction format. 6) Single-cycle instruction execution. 7) Hardwired rather than micro programmed control.

• Other characteristics of a RISC architecture 1) A relatively large number of registers in the processor unit. 2) Use of overlapped register windows to speed-up procedure call and return 3) Efficient instruction pipeline. 4) Compiler support for efficient translation of high-level language programs into machine language programs. Overlapped Register Windows Time consuming operations during procedure call Saving and restoring registers. Passing of parameters and result. Overlapped Register Windows Provide the passing of parameters and avoid the need for saving and restoring register values by hardware.

Concept of overlapped register windows : Total 74 registers : R 0 -R 73 R 0 -R 9 : Global registers R 10 -R 63 : 4 windows Window A , Window B, Window C, Window. D. in this 4 sets of window there are 10 locals registers + 2 sets of 6 registers. (Example)Procedure A calls procedure B R 26 -R 31 Store parameters for procedure B Store results of procedure B R 16 -R 25 : Local to procedure A R 32 -R 41 : Local to procedure B Window Size = L + 2 C + G = 10 + ( 2 X 6 ) + 10 = 32 registers Register File (total register) = (L + C) X W + G = (10 + 6 ) X 4+ 10 = 74 registers G: Global registers = 10 L: Local registers = 10 C: Common registers = 6 W: Number of windows = 4