Structured Logic Design With VHDL Ivan Dugic idugicverat

Structured Logic Design With VHDL Ivan Dugic idugic@verat. net Veljko Milutinovic vm@etf. bg. ac. yu School of Electrical Engineering University of Belgrade Department of Computer Engineering

Reference l James R. Armstrong, F. Gail Gray Structured Logic Design with VHDL, PTR Prentice Hall 1993. Ivan Dugic 2/72

Introduction l l VHDL - VHSIC Hardware Description Language VHSIC - Very High Speed Integrated Circuit l Development of a hardware description language model as a step in digital design at a high level of abstraction l Development of VHDL began in 1983, sponsored by Department of defense, further developed by the IEEE and released as IEEE Standard 1076 in 1987 l Today it is De facto industry standard for hardware description languages Ivan Dugic 3/72

Structured Design Concepts Ivan Dugic

The abstraction hierarchy Structured Design Concepts l l l The abstraction hierarchy employed by digital designers is a set of interrelated system representation Can be expressed in two domains: structural domain, behavioral domain Structural domain – component model is described in terms of an interconnection of more primitive components Behavioral domain – component model is described by defining its input/output response VHDL is used for behavioral description Ivan Dugic 5/72

The abstraction hierarchy Structured Design Concepts l Six abstraction hierarchy levels of detail commonly used in design: silicon, circuit, gate, register, chip and system Ivan Dugic 6/72

Representations Structured Design Concepts l l l Design representations can be either pictorial or textual Pictorial forms (used for structural description): block diagrams, timing diagrams, state tables etc. Textual methods of representation (used for behavioral description): natural languages (e. g. , English), equations (e. g. , Boolean) and computer languages (Hardware Description Language) Pictures are better for illustrating interrelationships Text is better for representing complex behavior Excessive use of either pictures or text result in a loss of perspective – “one cannot see the forest for the trees. ” Ivan Dugic 7/72

Structured Design Concepts l l Types of behavioral descriptions Two types of behavioral description – algorithmic and data flow Algorithmic – a procedure or program defining the I/O response with no implies of any particular physical implementation Data flow – a behavioral description in witch the data dependencies is the description match those in a real implementation Algorithmic and data flow descriptions are HDL implementations of behavior at the chip and register levels respectively Ivan Dugic 8/72

Design process Structured Design Concepts l l Design – a series of transformations from one representation of a system to another until a representation exists that can be fabricated The design cycle consists of a series of transformations - synthesis steps: (1) Transformation from English to an algorithmic natural language synthesis (2) Translation from an algorithmic representation to a data flow representation or to a gate level representation algorithmic synthesis Ivan Dugic 9/72

Design process Structured Design Concepts (3) Translation from data flow representation to a structural logic gate representation logic synthesis (4) Translation from logic gate to layout and circuit representation layout synthesis l The design cycle steps can be carried out automatically in all stages except the first that is currently an active area of research Ivan Dugic 10/72

Design process Structured Design Concepts Ivan Dugic 11/72

Structural design decomposition Structured Design Concepts l l The structural form of the design hierarchy implies a design decomposition process Two types of design: full tree design and partial tree design Ivan Dugic 12/72

Structural design decomposition Structured Design Concepts Difference – in the full tree design all behavior is specified at the same level, in partial tree design at different levels l Partial tree design is encountered because one frequently wants to evaluate the relationships between system components before they have been completely designed l Two concepts of tree design: top-down and bottom-up l l l Digital design is carried out in order to meet some objective criterion Major criteria concerning design and fabrication process: speed, chip area, cost Ivan Dugic 13/72

The digital design space Structured Design Concepts l Major criteria can be considered to be dimensions in Digital Design Space, with different tracks for various designs l Example - circuits A and B implement the same logic function, circuit A uses less area then B but is slower Ivan Dugic 14/72

Design tools Ivan Dugic

Design tools CAD tool taxonomy l l CAD tool – a software program used in the design process which assists in performing or automates a particular design function CAD tool taxonomy breaks tools down into classes and sub classes Ivan Dugic 16/72

Design tools CAD tool taxonomy Ivan Dugic 17/72

Design tools CAD tool taxonomy Editors – textual (circuit level – SPICE gate, register, chip – VHDL) or graphic (used at all levels) l Simulators – stochastic (system level, determines for example the percentage of time that a particular unit is busy) or deterministic (all levels above the silicon level) l Checkers and Analyzers – employed at all levels, used for example to insure that the layout implies a circuit that can be fabricated reliably (rule checkers), to check for the longest path through a logic circuit or system (timing analyzers) l Optimizers and Synthesizers – improving a form of the design representation l Ivan Dugic 18/72

Design tools l l l Schematic editors Editors that can be used to create and display an interconnected set of graphic tokens correspond to structural primitives Also creates a simulation model Typical editor features: (1) Library of primitive symbols including a simulation model corresponding to each primitive Primitives – native (fundamental logic elements e. g. , ANDs and ORs), standard parts families (e. g. , TTL, CMOS, ECL) Library can be extended with new symbols Ivan Dugic 19/72

Design tools Schematic editors (2) A system of graphic windows which can be used to create an interconnect of graphic tokens (3) Commands for creating wire lists Ivan Dugic 20/72

Design tools Simulators l l l Major tools used in the development of digital systems Programs which models the response of a system to input stimuli Modeling approach – system is modeled in interconnected net of digital elements, mapping the function of a digital logic element onto one or more processes Ivan Dugic 2172

Design tools Simulators l Process – computational entity which models the function and delay of the digital device Ivan Dugic 22/72

Design tools Simulators l l A network of devices is modeled by a network of processes A wire between devices in the digital network is modeled by a signal in the process network Ivan Dugic 23/72

Design tools Simulators l l The simulator operates on the network of processes – tracking process responds to signal transactions on its inputs These transactions are kept in the simulator time queue as a two-tuple forms (Signal. Name, Value) Ivan Dugic 24/72

Design tools Simulators l Simulation efficiency – very important when simulating large systems, defined as E = real_logic_time / host_CPU_time – time of simulation process l l Complete simulation of complicated VLSI system on conventional processors can literally require months (and even years!) Various simulation engines are developed enforcing parallel processing Ivan Dugic 25/72

Design tools Simulators l An example of complete simulation system Ivan Dugic 26/72

Design tools Synthesizers l l Used either to automate a design step or to provide assistance during the performance of a design step A computer program that automatically performs a translation from one design representation to another or a program that assists a human in making the translation Ivan Dugic 27/72

Design tools Synthesizers l l The process of optimizations is usually performed An optimization example Ivan Dugic 28/72

Design tools Synthesizers l l Specialized for a particular line of component or particular company and are often restricted in availability due to industrial proprietary interests High level synthesizer translates a representation of a circuit at a high level abstraction into a lower level of abstraction e. g. , algorithmic to gate Low level synthesizer gate to algorithmic Data flow synthesizer data flow to lower level Ivan Dugic 29/72

Basic Feature of VHDL Ivan Dugic

Design entities Basic Features of VHDL l l In VHDL a represented logic circuit is represented as a design entity A design entity consists of two different types of description: interface description and one or more architectural bodies Ivan Dugic 31/72

Design entities Basic Features of VHDL l l The description of interface signals includes the mode of the signal (i. e. , in or out) and the type of the signal, in previous case 3 -bit and 2 -bit vectors The truth table has been inserted as a comment – any line beginning with two dashes is interpreted as a comment Ivan Dugic 32/72

Architectural bodies Basic Features of VHDL l l l Architectural bodies are specifying the behavior of the entity Two types: algorithmic, structural Algorithmic - at the beginning of the design process, designers usually would like to check the accuracy of the algorithm without specifying the detailed implementation Ivan Dugic 33/72

Architectural bodies Basic Features of VHDL Ivan Dugic 34/72

Architectural bodies Basic Features of VHDL l Structural - the logic design stage l Used design hierarchy in ONES_CNT: Ivan Dugic 35/72

Architectural bodies Basic Features of VHDL l This architectural design implies the existence of MAJ 3 and OPAR 3 gates at the hardware level architectural MACRO of ONES_CNT is begin C(1) <= MAJ 3(A); C(0) <= OPAR 3(A); end MACRO; Ivan Dugic 36/72

Architectural bodies Basic Features of VHDL l MAJ 3 and OPAR 3 are decomposed into AND and OR gates Ivan Dugic 37/72

Model testing Basic Features of VHDL l l VHDL models must be tested Testing is performed by forming a top level entity called a test bench Ivan Dugic 38/72

Model testing Basic Features of VHDL Ivan Dugic 39/72

Model testing Basic Features of VHDL l l TEST_BENCH entity declaration contains no port statements – the test signals are generated internal to the test bench The result of simulating this test bench: Ivan Dugic 40/72

Block statements Basic Features of VHDL l A basic element of a VHDL description is the block Block. Name: block ----Inner block declaration section ---begin ----Inner block executable statements ---end block Block. Name; Ivan Dugic 41/72

Block statements Basic Features of VHDL l Block nesting is possible Ivan Dugic 42/72

Block statements Basic Features of VHDL l l GUARD Boolean condition can be associated with the block (CON = ‘ 1’) When FALSE enables certain types of statements inside the block – guarded statements (O 1 <= guarded I 1; ) Ivan Dugic 43/72

Block statements Basic Features of VHDL l Any guarded statement will be executed when (1) The guard is TRUE and a signal on the right hand side changes (2) The guard changes from FALSE to TRUE Ivan Dugic 44/72

Basic Features of VHDL Processes l Process is another major modeling element in VHDL Process. Name ( sensitivity list of signals ) l l Example – MAJ 3(A) Whenever a signal in sensitivity list changes, the process is activated Ivan Dugic 45/72

VHDL lexical description Basic Features of VHDL l l ASCII character code set is used in VHDL Character set – upper case A…Z, lower case letters a…z, digits 0 -9, special characters Ivan Dugic 46/72

VHDL lexical description Basic Features of VHDL l User defined identifiers – sequence of characters that starts with a letter and includes only letters, digits and isolated underline characters, different from VHDL reserved words Ivan Dugic 47/72

VHDL lexical description Basic Features of VHDL l l Comment – begins with two dashes, extra dashes can enhance readability Character literals – one character between two apostrophe delimiters – ‘A’, ‘ ‘, etc. String literals – sequence of printable characters between two quotation delimiters Long string literals exceeding the capacity of line must be concatenating by shorter strings, using the & character “A simple string literal. ” “ “ “A” “This is a very long string… “it requires concatenation” Ivan Dugic -- length= 24 -- length =0 --different from ‘A’ and” & 48/72

VHDL lexical description Basic Features of VHDL l l Bit string literal – real and integer Consists of a string of digits appropriate for the base, enclosed by quotation delimiters and preceded by a base specifier, B (binary), O (octal), X (hexadecimal) B” 11011110” O” 742” X”DE” l l Decimal literal – real and integer The exponent part of the literal is preceded by letter E, no spaces allowed Ivan Dugic 49/72

Basic Features of VHDL Data types l l Strong typed language Four classes of data types – scalar, composite, access, file Scalar data types – enumeration, numeric, physical data types Composite data types – arrays, records Ivan Dugic 50/72

Scalar data types Basic Features of VHDL l Enumeration data types type Enumeration. Type. Name is (value 1, …value. N); l Example type COLOR is (RED, ORANGE, YELLOW, GREEN, BLUE, INDIGO, VIOLET); l Specific number for every value – RED is 0, VIOLET is 6 Ivan Dugic 51/72

Scalar data types Basic Features of VHDL l l Different attributes can be used, for example “pos”, ”left”, ”right”, ”low”. ”high”, ”pred”, ”leftof”, ”rightof” etc. Attributes names are attached to the type name using the apostrophe, sometimes called “tick” character – some examples follow COLOR’pos(GREEN) = 3 COLOR’leftof(GREEN) = yellow etc. l Subtypes declaration do not define a new type – simply contain the values of the specified type subtype LONGWAVE is COLOR range COLOR’left to YELLOW; Ivan Dugic 52/72

Scalar data types Basic Features of VHDL l Numeric Data Types – Integer and Real type Numeric. Data. Type. Name is range value 1 to(downto) value. N; l Example type COUNTER is range 0 to 100; type PROBABILITY is range 0. 0 to 1. 0; l Attributes, subtypes can be used as in scalar data types Ivan Dugic 53/72

Scalar data types Basic Features of VHDL l l A physical data type is a scalar numeric data type with an associated system of units, such as time, length, voltage, current etc. TIME is only predefined physical data type, defined as follows type TIME is range units fs; ps = 1000 fs; ns = 1000 ps; us = 1000 ns; ms = 1000 us; sec = 1000 ms; Ivan Dugic 54/72

Scalar data types Basic Features of VHDL (continued) min = 60 sec; hr = 60 min; end units; Ivan Dugic 55/72

Composite data types Basic Features of VHDL l Arrays type Array. Name is array(value 1 to(downto) value. N) of Array. Type; type Array. Name is array (POSITIVE(NATURAL) range <>) of Array. Type; l For example type REGISTER_32_BIT is array (31 downto 0) of BIT; Ivan Dugic 56/72

Composite data types Basic Features of VHDL l Two predefined data types – STRING (array of CHARACTERs), BIT_VECTOR (array of BITs) type STRING is array (POSITIVE range <>) of CHARACTERS; type BIT_VECTOR is array (NATURAL range <>) of BIT; l The effect is that a user may specify the range when declaring an entity or type STRING – notation <> means unconstrained Ivan Dugic 57/72

Composite data types Basic Features of VHDL l Records - composite types with heterogeneous elements l For example type DATE is record DAY : INTEGER range 1 to 31; MONTH: MONTH_NAME; YEAR : INTEGER range 0 to 3000; end record; Ivan Dugic 58/72

Classes of objects Basic Features of VHDL l l There are three classes of data objects – constant, variable, signal Declaration of data objects constant Constant. Name: Data. Type : = value; variable Variable. Name: Data. Type : = initial_value; signal Signal. Name: Data. Type : = initial_value; l All ports must be signals Ivan Dugic 59/72

Assignment statements Basic Features of VHDL l l Variable assignment is different from signal assignment – in the first case it is used delimiter : =, in second <= Some examples STAR_COLOR : = GREEN; BETA_LEVEL : = 0. 5; X 1 <= ’ 1’ after 10 ns; SR 1 <= 5 after 5 ns; X 2 <= ’ 0’ after 10 ns, ’ 1’ after 20 ns, ’ 0’ after 30 ns; X 5 <= ’ 1’; Ivan Dugic 60/72

Assignment statements Basic Features of VHDL l Delta time – VHDL signals in order to correctly represent physical quantities do not change instantaneously Ivan Dugic 61/72

Signal variables Basic Features of VHDL l l The VHDL language predefines several attributes for signals: “active”, ”event”, ”stable”, “quiet”, “last_event”, “last_active”, “last_value”, “delayed” Examples X 2’active –- TRUE when a transaction occurs on X 2’event -- TRUE when an event occurs on X 2 X 1’stable –- TRUE unless there is an event Ivan Dugic 62/72

Signal variables Basic Features of VHDL X 1’stable(5 ns) –- TRUE when there has been no events on signal X 1 -- during the past 5 ns X 3’quiet -- TRUE unless there is a transaction on signal -- X 3 X 1’last_event -- has a value equal to the amount of time that has -- elapsed since last event on X 1 X’delayed(5 ns) -- defines a signal equal to X 1 delayed by 5 ns Ivan Dugic 63/72

Operators and expressions Basic Features of VHDL l l l Logic operators – on variables or signals of BIT or BOOLEAN type /= means not equal to ** exponentiation Ivan Dugic 64/72

Control statements Basic Features of VHDL l Control statements – sequential, parallel Ivan Dugic 65/72

Sequential control statements Basic Features of VHDL l Wait statement wait on Signal. Name[, Signal. Name] until Expression for Time; l Example wait on Z, Y until Z=0 for 100 ns; l l l If an event occurs on X or Y prior to 100 ns, then “Z=0” is evalueted. If “Z=0” is TRUE when the event on X or Y occurs, then the process will resume at the time, otherwise suspension occurs. The statement suspends execution of the process for maximum of 100 ns The process resumes after 100 ns has passed or when an event occurs on X or Y with Z=0. Ivan Dugic 66/72

Sequential control statements Basic Features of VHDL l If statement if Condition then Sequence. Of. Statements elseif Condition then Sequence. Of. Statements … else Sequence. Of. Statements end if; Ivan Dugic 67/72

Sequential control statements Basic Features of VHDL l Example if A<0 then LEVEL : = 1; elseif A>1000 then LEVEL : = 3; else LEVEL : = 2; end if; Ivan Dugic 68/72

Sequential control statements Basic Features of VHDL l Case statement case Expression is when Choices => Sequence. Of. Statements … when others => Sequence. Of. Statements end case; l Example case A+B is when 0 => X <= ”ZERO” when (1 to 20) => X <= ”POSITIVE” when others => X <= ”NEGATIVE” end case; Ivan Dugic 69/72

Sequential control statements Basic Features of VHDL l Loop statement -- Simple loop Sequence. Of. Statement end loop; -- FOR loop for Name in Range loop Sequence. Of. Statement end loop; -- WHILE loop while Condition loop Sequence. Of. Statement end loop; Ivan Dugic 70/72

Sequential control statements Basic Features of VHDL l Example loop compute (x); exit when x<10; end loop; for I in 1 to 10 loop A(I) : = A(I) + 1; end loop; while A<B loop A : = A + 1; end loop; Ivan Dugic 71/72

Sequential control statements Basic Features of VHDL l l Next statement Used to terminate the current loop iteration if a given condition is true next [Loop. Label] [when Condition]; l Exit statement l Similar to the “next” except that the entire loop statement is terminated exit [Loop. Label] [when Condition]; l l Null statement Does nothing, useful in case statements – if no action is desired for certain choices Ivan Dugic 72/72