Structure of Computer Systems Course 12 RISC architecture

Structure of Computer Systems Course 12 RISC architecture

CISC v. s. RISC Ø Ø Ø CISC – Complex Instruction Set Computer RISC - Reduced Instruction Set Computer Historical perspective: l l at first computers had a limited instruction set because of technological limitations (number of switching elements was limited) as integration technology improved: • • l more instructions were included in the set of a computer more complex operations implemented in instructions => more complex instructions consequences: • • • CPU became more and more complex CPU became slower (relative to the clock frequency) higher CPI and limited clock frequency

CISC Ø Reasons for complex instruction set computers l more powerful instructions • e. g. floating point arithmetic instructions l assembly language instructions closer to high level language instructions • e. g. loops, complex conditional jumps l more complex addressing modes, as support for complex data structures • addressing: indexed, based, mixed, scaled, etc. Ø Benefits: l l easier programming in assembly language less instructions needed to write an application easier compilation of high level languages support for complex data structures

CISC Ø Statistical measurements (during the ’ 70 s) l l Ø Surprising results l l l Ø which instruction types are more often used in different types of applications ? does the programmers use the available complex instructions? programmers prefer simple instructions complex instructions are used just occasionally, for some very specific operations (e. g. sine, arc tang. log, exponential, etc. ) most of the time the processor is executing simple instructions from a limited set Conclusion: l l the speed limitation caused by a complex instruction set is not justified let’s do things simpler and faster

RISC Ø Ø RISC = Reduced Instruction Set Computer Principle: sacrifice everything for speed l l l reduce the number of instructions – make CPU simpler get rid of complex instructions, which may slow down the CPU use simple addressing modes – less time spent to compute the address of an operand limit the number of accesses to the memory if a given operation cannot be executed in one clock period than do not implement it in an instruction extensive use of pipeline architecture – in order to reach CPI=1 (one instruction per clock period)

RISC - Main features Ø limited number of instructions in the instruction set: l Ø no complex instructions l Ø every instruction executes only one operation instructions have fixed format l l Ø 30 -40 instructions v. s 100 -200 in case of CISC fixed length few combinations of fields inside the instruction code instructions executed in one clock period (except Load and Store instructions) l l through intensive use of pipeline architecture every instruction have the same number of pipeline stages

RISC - Main features Ø Increased set of general purpose registers l l l Ø e. g. 32 -64 registers instructions operating with registers are executed in the shortest time compensate the lack of instructions operating with the memory Use of multiple register sets l l fast and easy context switch use of register set windows

RISC - Main features Ø Only two instructions operate (have access) to the memory locations: l l l Load – read data from the memory into a register Store – write the data from a register into the memory Load and Store instructions require two accesses to the memory: • one to read the instruction code • one to read or write the data l l Load and store instructions are the only instructions which are executed in two clock periods all the other instructions from the set are operating with registers or a register and a constant

RISC - Main features Ø Hard to write applications in assembly language l Ø A program on a RISC is more optimized than the same program written on a CISC l Ø lack of more powerful instructions and addressing modes only those operations are used which are strictly necessary More effort for programming, less time in execution l it is worth to have a greater time spent on programming if at the end the program will be executed many times in a shorter time !?

RISC - Main features Ø The CPU implemented in pure hardware (no microprogramming) l l instructions are decoded and executed using hardware components higher speed less execution steps Ø Compilers are more difficult to implement

RISC v. s. CISC Parameter RISC CISC Instruction types Simple Complex Number of instructions Reduced (30 -40) Extended (100 -200) Duration of an instruction One cycle More cycles (4 -120) Instruction format Fixed Variable Instruction execution In parallel (pipeline) Sequential Addressing modes Simple Complex Instructions accessing the memory Two: Load and Store Almost all from the set Register set multiple unique Complexity In compiler In CPU (micro-program)

Performance of RISC v. s. CISC: less 4 -100 long execution time = no_instructions*CPI*Tclk RISC: more 1 short ØHard to tell which is the best ØA combination of CISC and RISC may be the solution: ØRISC inside, CISC outside – see Pentium processors Øcomplex instructions translated into simple (RISC) instructions

Examples of RISC architectures Ø Academic implementations: l l Ø First commercial implementations l l l Ø RISC I si II – Berkley University (prof. Patterson, 1980) MIPS – Univ. Stanford (prof. Hennessy, 1982) IBM 801 – compania IBM (1975) ALPHA – compania DEC SPARC – Sun Microsystems (1987) General purpose processors: l l Power. PC – IBM si Motorola ARM architecture

Applications of RISC architectures Ø Powerful Workstations l Ø High-end graphical stations l Ø used for control applications and peripheral devices Digital signal processors l Ø used for simulation, animation, etc. Microcontrollers l Ø used for engineering purposes (ex. Sun station) used for signal processing Mobile devices l i. PAD, tablet, support for Android systems

RISC architecture examples MIPS Ø MIPS – q q l l l Microprocessor without Interlocking Pipe Stages or Million Instruction per Second processor: developed by Prof. Hennessy at Stanford University (1982) a classical pipeline architecture used as reference for teaching basic concepts about computers features: • 32 internal registers • reduced instruction set • instructions with fixed length (4 bytes); types: R, J, I • 3 operands instructions (source, destination, target) • (see a previous course for details)

RISC architecture examples Microcontrollers Ø Microcontroller l all components of a micro-computer system in a single integrated circuit: • • l CPU program memory data memory parallel I/O ports serial ports timers, counters converters: ADC, DAC, PWM watchdog used for control applications: • monitoring • feedback control

RISC architecture examples Microcontrollers Ø Example PIC 16 Fxx l l l CPU – simple, RISC architecture Instruction format – fixed, 14 bits/instruction only 35 instructions data format: 8 bits Internal memory – inside the chip - Harvard architecture – data separated from instructions • data memory – 368 bytes SRAM, organized on banks • instruction memory – 8 kinstructions Data memory • 256 bytes EEPROM (non-volatile memory) 0 Ports Interfaces: area • serial UART and SPI • Convertors: 10 bits ADC with 8 channel multiplexer • 3 timers • parallel ports l l ICD – In Circuit debug functionality Package: 28, 40 or 44 pins 1 Fh General registers User data area Bank 0 General registers User data area Bank 1 2, 3

RISC architecture examples Power. PC Ø Power. PC = Performance Optimization With Enhanced RISC – Performance Computing l l l l designed as a competitor for the Intel X 86 processor family developed by Apple, IBM and Motorola (1991) as an open architecture extension of the IBM’s Power architecture RISC and superscalar architecture initially intended for PCs, now used for embedded and high performance computers 32 and 64 bit processors many versions: Power. PC 601, 602, 604, 620, 74000 computers made with Power. PC: • • • Macintosh, Apple RS 6000, (RISC System 6000), IBM embedded computers