- Slides: 21
Static Timing Analysis - II Sushant Singh
RECAP: Setup check with Ideal clock
Insertion of Clock Tree : Non - ideal Clocks
What are real clocks: • Clock Tree is an essential process to minimize skew in the design. • Whenever Clock Tree is inserted, clock path becomes real. We also have network launch insertion delay and capture insertion delay. • All the timing parameters (Ghz) should be satisfied with real clocks. The chip should run at the specified frequency despite additional constraints.
Modification of Clock Path:
Clock Network Delay shifts the edges:
Skew should be zero:
Setup Constraints with real clocks:
Data Arrival and Data Required Time:
Adding speed breakers (x): degrades Slack
Solving a local problem might adversely affect globally
Increasing DRT affects DAT in the next cycle: • Increasing number of buffers in the capture clock increases DRT and helps DAT to meet timing (increasing slack). • But it degrades the DAT or slack of the next clock cycle. • Be sure to check timing (slack) of the next cycle before adding buffers to meet timing of the current clock path. • Solving constraints locally might adverse the timing globally.
Hold Analysis revisited for single clock:
Hold vs Setup Check: • Recall that hold check is done on the same edge at both launch and capture flops. • Setup check is done on different edges at both flops. • Hold failure leads to functional failure and setup check leads to incorrect capture of data or metastability.
Hold Time constraints with Real clocks:
Adding Necessary Hold Time constraints (pessimism):
Increasing slack in Hold Timing Constraints:
Increasing skew leads to increase in DRT, which results in Hold timing violation.