State Machine Timing z Retiming y Slosh logic

State Machine Timing z Retiming y Slosh logic between registers to balance latencies and improve clock timings y Accelerate or retard cycle in which outputs are asserted z Pipelining y Splitting computations into overlapped, smaller time steps CS 150 - Fall 2005 – Lec #16 – Retiming - 1

Recall: Synchronous Mealy Machine Discussion z Placement of flipflops before and after the output logic changes the timing of when the output signals are asserted … Synchronizer Circuitry at Inputs and Outputs CS 150 - Fall 2005 – Lec #16 – Retiming - 2

Recall: Synchronous Mealy Machine with Synchronizers Following Outputs Case III: Synchronized Outputs Signal goes into effect one cycle later A asserted during Cycle 0, ƒ' asserted in next cycle Effect of ƒ delayed one cycle CS 150 - Fall 2005 – Lec #16 – Retiming - 3

Vending Machine State Machine z Moore machine y outputs associated with state N’ D’ + Reset 0¢ [0] Mealy machine outputs associated with transitions 0¢ N’ D’ N D 5¢ [0] D N’ D’ D/0 5¢ N’ D’/0 10¢ N’ D’/0 15¢ Reset’/1 N/0 N’ D’ D/1 N+D 15¢ [1] N’ D’/0 N 10¢ [0] (N’ D’ + Reset)/0 Reset/0 N+D/1 Reset’ CS 150 - Fall 2005 – Lec #16 – Retiming - 4

State Machine Retiming z Moore vs. (Async) Mealy Machine y Vending Machine Example Open asserted only when in state 15 CS 150 - Fall 2005 – Lec #16 – Retiming - 5 Open asserted when last coin inserted leading to state 15

State Machine Retiming z Retiming the Moore Machine: Faster generation of outputs z Synchronizing the Mealy Machine: Add a FF, delaying the output z These two implementations have identical timing behavior Push the AND gate through the State FFs and synchronize with an output FF Like computing open in the prior state and delaying it one state time CS 150 - Fall 2005 – Lec #16 – Retiming - 6

State Machine Retiming z Effect on timing of Open Signal (Moore Case) Clk State FF prop delay Out prop delay Open Retimed Open Calculation Out calc Plus set-up NOTE: overlaps with Next State calculation CS 150 - Fall 2005 – Lec #16 – Retiming - 7

State Machine Retiming z Timing behavior is the same, but are the implementations really identical? FF input in retimed Moore implementation Only difference in don’t care case of nickel and dime at the same time CS 150 - Fall 2005 – Lec #16 – Retiming - 8 FF input in synchronous Mealy implementation

Pipelining Principle z Pipelining review from CS 61 C: Analog to washing clothes: step 1: wash (20 minutes) step 2: dry (20 minutes) step 3: fold (20 minutes) 60 minutes wash dry fold x 4 loads 4 hours load 1 load 2 load 3 load 4 20 min overlapped 2 hours CS 150 - Fall 2005 – Lec #16 – Retiming - 9

Pipelining wash load 1 load 2 load 3 load 4 dry load 1 load 2 load 3 load 4 fold load 1 load 2 load 3 load 4 • Increase number of loads, average time per load approaches 20 minutes • • Latency (time from start to end) for one load = 60 min Throughput = 3 loads/hour • Pipelined throughput # of pipe stages x un-pipelined throughput. CS 150 - Fall 2005 – Lec #16 – Retiming - 10

Pipelining z General principle: Assume T = 8 ns TFF(setup +clk q) = 1 ns F = 1/9 ns = 111 MHz z Cut the CL block into pieces (stages) and separate with registers: T’ = 4 ns + 1 ns + 4 ns +1 ns = 10 ns F = 1/(4 ns +1 ns) = 200 MHz Assume T 1 = T 2 = 4 ns z CL block produces a new result every 5 ns instead of every 9 ns CS 150 - Fall 2005 – Lec #16 – Retiming - 11

Limits on Pipelining z Without FF overhead, throughput improvement proportional to # of stages • • After many stages are added. FF overhead begins to dominate: Other limiters to effective pipelining: • • • Clock skew contributes to clock overhead Unequal stages FFs dominate cost Clock distribution power consumption feedback (dependencies between loop iterations) CS 150 - Fall 2005 – Lec #16 – Retiming - 12 FF “overhead” is the setup and clk to Q times.

Pipelining Example z F(x) = yi = a xi 2 + b xi + c z Computation graph: z x and y are assumed to be “streams” z Divide into 3 (nearly) equal stages. z Insert pipeline registers at dashed lines. z Can we pipeline basic operators? CS 150 - Fall 2005 – Lec #16 – Retiming - 13

Example: Pipelined Adder z Possible, but usually not done … (arithmetic units can often be made sufficiently fast without internal pipelining) CS 150 - Fall 2005 – Lec #16 – Retiming - 14

State Machine Retiming Summary z Retiming y Vending Machine Example x. Very simple output function in this particular case y But if output takes a long time to compute vs. the next state computation time -- can use retiming to “balance” these calculations and reduce the cycle time z Pipelining y Introduce registers to split computation to reduce cycle time and allow parallel computation y Trade latency (number of stage delays) for cycle time reduction CS 150 - Fall 2005 – Lec #16 – Retiming - 15