State Machine Design 397 FSM Gray code counter

FSM 설계 예(Gray code counter) Gray code encoder State diagram Based on state table

§ FF Input equations => D 0 = !Q 2 !Q 1 + Q

그레이 코드 카운터의 FSM VHDL Enumerated type : User-defined type in VHDL Enumerated State

열거형(Enumerated Type) 예 TYPE DIRECTION IS (up, down, left, right); Þ다음으로 type DIRECTION을 position(임의의

Note the Output Assignments are made outside of the Process Concurrently 409

§ State table § Flip-flop excitation table § State diagram J = /Q •

Synchronized with system clock Asynchronized with system clock 414

§ Modified circuit and Simulation results Synchronized with system clock 415

단발 펄스 발생기(Single Pulse Generator) § State diagram § State table present state input

수정된 단발 펄스 발생기 Synchronized with system clock 421

쉬프트 레지스터 디바운스 회로 pb_in active-high synchronous load 10 ms 타이밍 값은 arbitrary value

미사용 상태 예(Two Pulse Generator) Two-pulse generator States (111), (110), (101), (100), (011) =>

0. 75 Hz N-S E-W Altera UP-1 25. 175 MHz N-S E-W Timer R

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상태 머신 설계 (State Machine Design) 397

FSM 설계 예(Gray code counter) Gray code encoder State diagram Based on state table 405

§ FF Input equations => D 0 = !Q 2 !Q 1 + Q 2 Q 1, D 1 = Q 1 !Q 0 + !Q 2 Q 0, D 2 = Q 1 !Q 0 + Q 2 Q 0 § Draw a circuit diagram 406

그레이 코드 카운터의 FSM VHDL Enumerated type : User-defined type in VHDL Enumerated State (type STATE_TYPE) 407

열거형(Enumerated Type) 예 TYPE DIRECTION IS (up, down, left, right); Þ다음으로 type DIRECTION을 position(임의의 이름)이름으로 signal을 정의 할 수 있다. SIGNAL position : DIRECTION; => IF문 이나 다른 구문으로 signal “position”에 type DIRECTION의 4가지 중 하나를 할당 할 수 있다. IF (x=‘ 0’ and y=‘ 0’) THEN position <= down; ELSIF (x=‘ 0’ and y=‘ 1’) THEN position <= left; ELSIF (x=‘ 1’ and y=‘ 0’) THEN position <= up; ELSE position <= right; END IF; 408

Note the Output Assignments are made outside of the Process Concurrently 409

411

제어입력을 갖는 FSM § Mealy machine 412

§ State table § Flip-flop excitation table § State diagram J = /Q • /in 1 + Q • /in 1 = /in 1 K=1 Out 1 = /Q • /in 1 Out 2 = Q • /in 1 + Q • in 1 = Q 413

Synchronized with system clock Asynchronized with system clock 414

§ Modified circuit and Simulation results Synchronized with system clock 415

상태 머신 펄서(SM Pulser) VHDL 416

단발 펄스 발생기(Single Pulse Generator) § State diagram § State table present state input next state sync. input output Q(t) sync Q(t+1) D pulse 0 0 1 1 0 1 D = /sync Pulse = /Q • /sync 1 0 1 0 1 0 0 0 Asynchronized with system clock 419

수정된 단발 펄스 발생기 Synchronized with system clock 421

쉬프트 레지스터 디바운스 회로 pb_in active-high synchronous load 10 ms 타이밍 값은 arbitrary value 임(무시) 426

Switch debouncer 434

미사용 상태 예(Two Pulse Generator) Two-pulse generator States (111), (110), (101), (100), (011) => Unconditional transition 표 10. 6, Fig. 10. 34 참조 D 2 = /Q 2 • Q 1 • Q 0 D 1 = /Q 2 • Q 1 • /Q 0 + /Q 2 • /Q 1 • /in 1 D 0 = /Q 2 • /Q 0 • in 1 + /Q 2 • /Q 1 • in 1 Out 1 = /Q 2 • Q 1 • Q 0 Out 2 = Q 2 • /Q 1 • /Q 0 436

Two pulse generator 조합회로 출력 437

미사용 상태 VHDL (Two Pulse Generator) 439

GDF VHDL 441

0. 75 Hz N-S E-W Altera UP-1 25. 175 MHz N-S E-W Timer R G G (s 0) Y (s 1) Y R (s 2) (s 3) (s 0) 443

MOD-5 카운터 TIMER 444