ST is a solution for sim test u

ST is a solution for sim　& test u Now, you have to　write various test benches for all simulators: – HDL, Netlist level – Circuit, SPICE level u ST is a solution!! – You can write your test bench with PERL!! – Your testbench can be converted to » Verilog » SPICE » LSI testers 2020/10/24 3

記述例: 　4ビット累算回路 #!/usr/local/bin/perl use ST; シミュレーション対象の定義 target "verilog"; module "fourbitaccum"; Verilog定義 vcd "fourbitaccum. vcd", 0; pin "in[3: 0]", "input"; pin "CLK", "clock"; ピンの定義 pin "RST", "input"; fourbitaccu pin "out[7: 0]", "output"; タイミングの定義 timing 1 e-09, 1 e-07, 10; m clock "CLK", "1111100000"; waveform 波形の定義 "input", "dnrz", "%. . ", "in", "RST"; waveform "output", "edge", ". . %", "out"; pinorder "in", "RST", "out"; beginvector; 入力ベクタ、期待値の定義 vector 0, 0, 0; vector 1, 1, 0; 2020/10/24 2000年VDECデザイナーズフォーラム＠広島 vector 5, 1, 1; endvector; 10

使い方と期待値比較: Verilogインタフェース 実行結果 期待値との照合結果 st. log 期待値との相違 Logファイル（VCS) Compiler version 5. 2; Runtime version 5. 2; Sep 22 09: 36 2000 Some simulation mismatches are detected! $finish at simulation time 400 cycle(time): pin: exp. val != sim. result 2(29): out: 2 !=1 3(39): out: 5 !=6 VCS Simulation Report Time: 400 ns 2020/10/24 13