ST 7 MICROCONTROLLER TRAINING 1 INTRODUCTION 2 CORE

ST 7 MICROCONTROLLER TRAINING 1 - INTRODUCTION 2 - CORE 3 - ADRESSING MODES 4 - PERIPHERALS 5 - ST 7 SOFTWARE TOOLS 6 - ST 7 HARDWARE TOOLS 7 - STVD 7 ST 7 PERIPHERALS 1

ST 7 I/O PORTS 8 -Bit CORE SP PCL PCH Interrupt Controller INT Accu Index X Index Y CC PORT l Ø Ø Ø Ø Ø 16 -bit timer Peripheral Program Peripheral ST 623 x BLOCK DIAGRAM Otp / Rom Peripheral Data Ram 256 bytes Peripheral Test/Vpp Peripheral Reset Data EEprom Optional features : Peripheral AD converter 16 -bit Timer 8 -bit Auto Reload Timer SPI SCI I 2 C EEPROM Programmable Op. Amp CAN Oscillator Power Supply Watchdog Timer Optional ST 7 PERIPHERALS 2

ST 7 I/O PORTS Overview l ALL THE I/Os ARE INDIVIDUALLY SOFTWARE CONFIGURABLE USING 3 DIFFERENT REGISTERS : Ø DDR: Ø OR: l Data Direction Register Data Register Option Register ST 72254 : 22 MULTIFUNCTION BIDIRECTIONAL I/O LINES Ø Ø Ø 18 Standard I/Os (sink up to 5 m. A) 8 High Current I/Os (PA 0 -PA 7 can sink up to 20 m. A) 6 Analog Inputs (PC 0 -PC 5) 16 alternate Functions on 16 pins (for Timers, SPI and I 2 C) All the I/Os can be set-up as Interrupt inputs ST 7 PERIPHERALS 3

ST 7 I/O PORT Safe I/O pin transition DDR OR Mode 0 0 Floating input 0 1 Input pull- up with/without interrupt 1 0 Output Open-Drain 1 1 Output Push-Pull 01 00 10 11 Reset State ST 7 PERIPHERALS 4

ST 7 I/O PORT Basic structure Read / Write DDRi Data Direction Register Bit Write DRi Latch Data Output bit Ouput I/O Pin Input Reg bit Read DRi Input I/O l SOFTWARE SELECTABLE CONFIGURATION l HIGH FLEXIBILITY for software and PC board layout ST 7 PERIPHERALS 5

ST 7 I/O PORT Settings & electrical behaviour l Configuration given when no external Hardware is connected the pins Input Floating Input Pull_up DDR 0 0 1 1 OR 0 0 1 1 Written DR 0 1 0 1 Floating Vdd Vss Floating Vss Vdd X X 1 1 0 1 I/O Pin Read DR ST 7 PERIPHERALS Ouput Open Drain Ouput Push-Pull 6

ST 7 EXTERNAL INTERRUPTS Pin 1 Pin 2 Interrupt Source 1 Edge/level selection Pin M ST 7 Interrupt Controller Pin 1 Pin 2 Interrupt Source 2 Edge/level selection Pin N Pin 1 Miscellaneous Register Pin 2 Interrupt generation Interrupt source Negative edge only Latched Positive edge only Latched Negative edge and low level Not Latched Positive and Negative edge Latched ST 7 PERIPHERALS 7

ST 7 I/O PORT Block Diagram REGISTER ACCESS ALTERNATE OUTPUT V DD 1 0 ALTERNATE ENABLE DR DATA BUS PULL-UP Condition OR PAD OR SEL DDR SEL CMOS SCHMITT TRIGGER 1 0 EXTERNAL INTERRUPT POLARITY SOURCE SELECTION FROM OTHER BITS ALTERNATE INPUT ST 7 PERIPHERALS ANALOG INPUT 8

PROGRAMMING TIPS I/O Port (1) l AD CONVERTION Ø Each pin used by the ADC cell must be configured as floating input (i. e. without pull-up resistors) before activating the analog input mode l ALTERNATE FUNCTION Ø A signal coming from an on-chip peripheral can be output on a port. In this case, the I/O is automatically configured in output mode. Ø A signal coming from an I/O can be an input to an on-chip peripheral. In this case, it must be configured as Input without interrupt (Floating Input). ST 7 PERIPHERALS 9

PROGRAMMING TIPS I/O Port (2) l Open Drain Outputs can be used for bus driving where several devices are connected on the same line. They can be wired together to increase current drive capability l Voltages driving an Analog Input should always stay within the absolute maximum ratings (Vss-0. 3 V to Vdd+0. 3 V) l Pull-up resistors typically deliver 50µA under 5 V l The toggling time on any output pin will be approximately 30 ns for a 50 p. F load ST 7 PERIPHERALS 10

I/O Ports Configuration Example PBDR 7 PBDR 0 Fill the dedicated I/O port registers in order to have the following configuration: l PB 0: PB 2 Ø Push-Pull Output (high level) PBDR PBDDR 7 l l Ø Floating Input PBDDR 0 l PB 5 Ø Input with Interrupt PBDDR PBOR 7 PB 3, PB 4 l PB 6 Ø Push-Pull Output (low level) PBOR 0 l PBOR PB 7 Ø Ouput (High Impedance) ST 7 PERIPHERALS 11

A/D CONVERTER 8 -Bit CORE SP PCL PCH Interrupt Controller INT Accu Index X Index Y CC PORT l Ø AD converter 16 -bit timer Ø Ø Ø Ø Peripheral Program Peripheral ST 623 x BLOCK DIAGRAM Otp / Rom Peripheral Data Ram 256 bytes Peripheral Test/Vpp Peripheral Reset Data EEprom Optional features : Peripheral Oscillator 16 -bit Timer 8 -bit Auto Reload Timer SPI SCI I 2 C EEPROM Programmable Op. Amp CAN Power Supply Watchdog Timer Optional ST 7 PERIPHERALS 12

ST 7 AD CONVERTER Overview (1) l 8 -BIT SUCCESSIVE APPROXIMATIONS CONVERTER WITH UP TO 8 ANALOG CHANNELS: Ø ST 72254 : 6 inputs Ø ST 72334 and ST 725 xx : 8 inputs Ø ST 72171 : 6 external inputs + 2 internal inputs l FEATURE : Ø Accuracy : 1 LSB Ø Total Unajusted Error MAX : 1 LSB Ø Conversion time : 24 CPU cycle ie 3µs at full speed (8 MHz) l FLAGS Ø COCO : end of conversion (Status flag) Ø ADON : ADC on/off bit (to reduce power consumption) ST 7 PERIPHERALS 13

ST 7 AD CONVERTER Overview (2) l LOW CONSUMPTION MODES Ø Wait mode doesn't affect the ADC Ø Halt mode stops the ADC. l HARDWARE Ø ST 72334 and ST 725 xx : Vdda and Vssa must be connected externally respectivelly to Vdd and Vss through decoupling capacitors. Ø ST 72254 : connection done internally l RATIONETRIC In the Functionnal Range Ø If analog voltage input > Vdd : converted result = FFh (no overflow indication) Ø If analog voltage input < Vss : converted result = 00 h (no underflow indication) ST 7 PERIPHERALS 14

ST 7 AD CONVERTER Block diagram COCO - ADON 0 - CH 2 CH 1 CH 0 (Control Status Register) CSR AIN 0 AIN 1 AIN 2 AIN 3 AIN 4 AIN 5 AIN 6 AIN 7 ANALOG MUX Fcpu SAMPLE & HOLD ANALOG TO DIGITAL CONVERTER AD 7 AD 6 AD 5 AD 4 AD 3 AD 2 AD 1 AD 0 (Data Register) DR ST 7 PERIPHERALS 15

PROGRAMMING TIPS AD Converter l PROCEDURE Ø Step 1 : The analog input pins must be set-up as Input no pull-up no interrupt Ø Step 3 : assign a channel for the conversion (bit CH 0, CH 1 and CH 2 in CSR register) and set the ADON bit Ø Step 4 : Wait until COCO bit set. A continuous conversion is performed. Ø To reach the best accuracy, the impedance seen by the analog input pin must be lower than 10 Kohm. ADON bit set Continuous ADC init : –IO config t = 3µs –Channel selected t = 3µs Write in CSR : ® Stop conversion If ADON still set : new conversion Else stop ADC t = 3µs Beginning of a new conversion by writing in the CSR (select the analog channel) ST 7 PERIPHERALS 16

ADC Configuration Example COCO ADON CH 3 CH 2 CH 1 CH 0 ADCDR l Fill ADCCSR register in order to have an analog conversion on AIN 4. l What bit has to be tested to know the end of the conversion ? ST 7 PERIPHERALS 17

ST 7 16 -bit TIMER 8 -Bit CORE SP PCL PCH Interrupt Controller INT Accu Index X Index Y CC PORT l 16 -bit timer Ø AD converter Peripheral Ø 16 -bit Timer Peripheral Program Peripheral ST 623 x BLOCK DIAGRAM Otp / Rom Ø Ø Ø Ø Peripheral Data Ram 256 bytes Peripheral Test/Vpp Peripheral Reset Data EEprom Optional features : Peripheral Oscillator 8 -bit Auto Reload Timer SPI SCI I 2 C EEPROM Programmable Op. Amp CAN Power Supply Watchdog Timer Optional ST 7 PERIPHERALS 18

16 -bit TIMER Overview (1) l 16 -bit free running counter driven by a software configurable prescaler l 4 different modes : Ø Input capture (2 pins) : to latch the value of the counter after a transition on the ICAPi pin Ø Output compares (2 pins) : to control an output waveform or to indicate when a period of time is over Ø One pulse : generation of a pulse when an external event occurs Ø PWM : generation of a signal with frequency and pulse length set by software (OCR 1 and OCR 2) ST 7 PERIPHERALS 19

16 -bit TIMER Overview (2) l The timer clock can be provided by : Ø The internal clock with a configurable ratio Ø An external source : Fext must 4 times slower than the internal clock (ie Fmax=2 Mhz) CC 1 CC 0 Timer clock 0 0 Fcpu/4 0 1 Fcpu/2 1 0 Fcpu/8 1 1 External ST 7 PERIPHERALS 20

16 -bit TIMER Block diagram ST 7 INTERNAL BUS OUTPUT COMPARE REGISTER 1 16 -BIT FREE RUNNING COUNTER ALTERNATE REGISTER 1/2 1/4 1/8 EXCLK INPUT CAPTURE REGISTER 1 16 LOW BYTE INPUT CAPTURE REGISTER 2 16 16 -Bit INTERNAL TIMER BUS OUTPUT COMPARE CIRCUIT OVERFLOW DETECT CIRCUIT 0 OCF 1 TOF ICIE OCIE TOIE FOLV 2 FOLV 1 OLVL 2 IEDG 1 OLVL 2 OCF 2 0 OC 1 E OC 2 E OPM CONTROL REGISTER 1 TIMER INTERNAL INTERRUPT EDGE DETECT CIRCUIT 2 ICAP 1 EDGE DETECT CIRCUIT 1 ICAP 2 0 ICF 1 ICF 2 HIGH BYTE LOW BYTE OUTPUT COMPARE REGISTER 2 16 CC 1 CC 0 STATUS REGISTER HIGH BYTE 8 8 -BIT BUFFER LOW BYTE EXEDG HIGH BYTE CPU CLOCK LOW BYTE MCU-PERIPHERAL INTERFACE ST 7 PERIPHERALS PWM CC 1 LATCH 1 OCMP 1 LATCH 2 OCMP 2 CC 0 IEDG 2 EXEDG CONTROL REGISTER 2 21

16 -bit TIMER Input capture (1) l Captures the counter value upon input signal edge detection l Allows an external pulse length measurement l Internal safety process in case of critical interrupts timing Timer Counter Register ICAP 1 A Edge Detector Input Capture Register Software Maskable Interrupt Request ST 7 PERIPHERALS 22

16 -bit TIMER Input capture (1) ICAP 1 (Control Register 1) CR 1 ICAP 2 EDGE DETECT CIRCUIT 1 ICIE IEDG 1 (Status Register) SR IC 2 R IC 1 R ICF 1 ICF 2 0 0 0 (Control Register 2) CR 2 16 -BIT FREE RUNNING COUNTER CC 1 ST 7 PERIPHERALS CC 0 IEDG 2 23

16 -bit TIMER Ouput compare (1) l Event generation (Interrupt request/bit toggling) whenever the compare register matches the counter l Indicates a period of time has elapsed and controls an output waveform l Internal safety process in case of critical interrupts timing Timer Counter Register Match? Software Maskable Interrupt Request Pulse generation Output Compare Register ST 7 PERIPHERALS 24

16 -bit TIMER Output compare (2) 16 -BIT FREE RUNNING COUNTER OC 1 E OC 2 E CC 1 CC 0 (Control Register 2) CR 2 16 -bit (Control Register 1) CR 1 OUTPUT COMPARE CIRCUIT 16 -bit OC 1 R OCIE OLVL 2 OLVL 1 Latch 1 OCMP 1 Latch 2 OCMP 2 16 -bit OC 2 R OCF 1 OCF 2 0 0 0 (Status Register) SR ST 7 PERIPHERALS 25

16 -bit TIMER Real Time Clock l l In each Interrupt Routine the OCR Register content is updated. There is no shift time (the counter is never reset externally). FREE RUNNING COUNTER VALUE FFFFh OCR+DT OCR 0000 h Timer IT ST 7 PERIPHERALS Timer IT time 26

16 -bit TIMER One pulse mode (1) l Generation of a pulse synchronized with an external event l Allows Phase Locked Loop Generation l On Input Capture event Ø The counter is reset Ø The timer output pin is toggled l On Output compare event Ø The timer output pin is toggled Ø The timer waits for the next Input Capture event ST 7 PERIPHERALS 27

16 -bit TIMER One pulse mode (2) l Free running counter is When a external event occurs on ICAP 1 pin initialized to FFFCh l OLVL 2 bit level is applied on the OCMP 1 pin l. I CF 1 bit is set When the free running counter reaches OC 1 R register value l OLVL 1 bit level is applied on the OCMP 1 pin ST 7 PERIPHERALS 28

16 -bit TIMER One pulse mode (3) FREE RUNNING COUNTER VALUE FFFFh FFFCh Compare 1 0000 h time ICAP 1 Input Capture pin Timer input time OCMP 1 Ouput Compare pin Timer output time ST 7 PERIPHERALS 29

16 -bit TIMER PWM mode (1) l Automatic generation of a Pulse Width Modulated signal l Period &pulse lenght set by software: Ø The first Output Compare Register OC 1 R contains the length of the pulse Ø The second Output Compare Register OCR 2 contains the period of the pulse l Resolution up to 100 steps at 20 KHz (f. CPU =4 MHz): 1% of accuracy on the duty cycle ST 7 PERIPHERALS 30

ST 7 TIMER PWM mode (2) l Free running counter is initialized to FFFCh When the free running counter reaches OC 2 R register value l OLVL 2 bit level is applied on the OCMP 1 pin l ICF 1 bit is set When the free running counter reaches OC 1 R register value l OLVL 1 bit level is applied on the OCMP 1 pin ST 7 PERIPHERALS 31

ST 7 TIMER PWM mode (3) FREE RUNNING COUNTER VALUE Tmax = Ttimer × 65535 FFFFh FFFCh Compare 2 Compare 1 0000 h time OLVL 2= 1 OCMP 1 Ouput Compare pin Timer output OLVL 1=0 ST 7 PERIPHERALS time 32

PROGRAMMING TIPS 16 -bit timer (1) l Define Input capture pins as inputs through the corresponding Data Direction Register l Read MSB first and then the LSB Ø The counter LSB is buffered during the MSB read Ø The counter LSB read accesses the buffered value Ø Any access to the high byte disables the corresponding timer function until the low byte is accessed Ø Disable the interrupts during any word access l Writing the counter LSB resets the timer at FFFCh ST 7 PERIPHERALS 33

PROGRAMMING TIPS 16 -bit timer (2) l Clearing a status bit is performed by a read access to the status register followed by an access (read or write) to the low byte of the corresponding register l The alternate counter register is always matching the counter l Use the alternate counter register when you do not want to clear the Timer Overflow Flag l No interrupt is generated on compare when the PWM is active, but the ICF 1 bit is set every period and can generates an interrupt l Be aware that the implicit reading performed by the emulator might clear the status flags ST 7 PERIPHERALS 34

PROGRAMMING TIPS 16 -bit timer (3) Read CHR CLR buffered ACHR ACLR buffered Any others Instructions Read CLR ACLR Write Returns the CLR buffered value Clear TOF bit Returns the ACLR buffered value CLR Reset counter to FFFCh Clear TOF bit ACLR Reset counter to FFFCh ST 7 PERIPHERALS 35

Timer Configuration Example ICIE OCIE TOIE FOLVL 2 FOLVL 1 OLVL 2 IEDG 1 OLVL 1 OC 1 E OC 2 E OPM PWM CC 1 CC 0 IEDG 2 EXED TACR 1 TACR 2 l Fill the Timer registers in order to generate a real time clock at 5 ms using an interrupt strategy & a timer clock at 1µs (f. CPU = 8 MHz). Ø An interrupt is generated every 5 ms using Output compare 1. Ø OCMP 1 pin has to be toggled every period l What is the value to add to the TAOC 1 HR & TAOC 1 LR every period? ST 7 PERIPHERALS 36

Serial Peripheral Interface 8 -Bit CORE SP PCL PCH Interrupt Controller INT Accu Index X Index Y CC PORT l Optional features : Ø AD converter Ø 16 -bit Timer Ø 8 -bit Auto Reload Timer 16 -bit timer Peripheral Program Peripheral ST 623 x BLOCK DIAGRAM Otp / Rom Ø SPI Peripheral Data Ram 256 bytes Ø Ø Ø Peripheral Test/Vpp Peripheral Reset Data EEprom Peripheral Oscillator SCI I 2 C EEPROM Programmable Op. Amp CAN Power Supply Watchdog Timer Optional ST 7 PERIPHERALS 37

ST 7 SPI Overview l THE SPI CELL ALLOWS A FULL DUPLEX SYNCHRONOUS SERIAL COMMUNICATION BETWEEN 2 DEVICES l MAIN FEATURE : Ø Full duplex, 3 wire synchronous transfers Ø Master : 6 frequency available. It rates up to 2 MHz Ø Slave mode : it rates up 4 MHz l THE CLOCK IS PROGRAMMABLE : POLARITY AND PHASE l 3 DIFFERENT STATUS FLAG : Ø Data transfer : data transfer completed Ø Write collision : access to SPIDR during a transmission Ø Fault flag : fault in master mode detected ST 7 PERIPHERALS 38

ST 7 SPI Master-Slave communication Master Slave 8 -bit Shift Register SPI Clock Generator MISO MOSI SCK 8 -bit Shift Register 5 V SS SS ST 7 PERIPHERALS 39

ST 7 SPI Block diagram SPIDR Read Internal Bus Read Buffer IT request MISO MOSI SPISR 8 -Bit Shift Register SPIF WCOL - MODF - - Write SPI STATE CONTROL SCK MISCR 2 SPIOD SSM SPICR MASTER CONTROL SPIE SPR 2 -MSTR CPOL CPHA SPR 1 SPR 0 SSI SERIAL CLOCK GENERATOR SS ST 7 PERIPHERALS 40

ST 7 SPI Single master configuration SS SCK SS SS SCK Slave MCU MOSI MISO SCK Slave MCU SS MOSI MISO 5 V SS P o r ts SCK Master MCU ST 7 PERIPHERALS 41

SPI Configuration Example SPIE SPR 2 MSTR CPOL CPHA SPR 1 SPR 0 SPICR l Fill the SPICR register in order to configure the SPI cell in Ø Ø Ø Master mode Serial clock at 5 OOKHz (f. CPU=8 MHz) Sampling on 2 nd edge High level after clock signal No interrupt generation ST 7 PERIPHERALS 42

ST 7 I 2 C 8 -Bit CORE SP PCL PCH Interrupt Controller INT Accu Index X Index Y CC PORT l Optional features : Ø Ø Ø 16 -bit timer Peripheral Program Peripheral ST 623 x BLOCK DIAGRAM Otp / Rom Peripheral Data Ram 256 bytes Peripheral Ø I 2 C Peripheral Test/Vpp Ø EEPROM Ø Programmable Op. Amp Ø CAN Peripheral Reset Data EEprom AD converter 16 -bit Timer 8 -bit Auto Reload Timer SPI SCI Peripheral Oscillator Power Supply Watchdog Timer Optional ST 7 PERIPHERALS 43

ST 7 I 2 C Overview l The I 2 C cell provides all I 2 C bus specific sequencing, protocol, arbitration and timing in order to reduce as much as possible the software overhead l Polling Management or Interrupt Driven Cell l Main feature : Ø Ø Multi Master capability Interrupt generation Standard I 2 C mode (up to 100 k. Hz) and Fast I 2 C mode (up to 400 k. Hz) 7 -bit and 10 -bit addressing ST 7 PERIPHERALS 44

ST 7 SCI 8 -Bit CORE SP PCL PCH Interrupt Controller INT Accu Index X Index Y CC PORT l Optional features : Peripheral Ø Ø Peripheral Ø SCI 16 -bit timer Peripheral Program Peripheral ST 623 x BLOCK DIAGRAM Otp / Rom Data Ram 256 bytes Ø Ø Peripheral Test/Vpp Peripheral Reset Data EEprom Peripheral Oscillator AD converter 16 -bit Timer 8 -bit Auto Reload Timer SPI I 2 C EEPROM Programmable Op. Amp CAN Power Supply Watchdog Timer Optional ST 7 PERIPHERALS 45

ST 7 SCI Overview (1) l FULL DUPLEX, ASYNCHRONOUS COMMUNICATION l DUAL BAUD RATE GENERATOR (MAXIMUM SPEED FOR SCI TX and RX : 250 k. Hz) Ftx = l Fcpu [16 × PR × 2] × TR Frx = Fcpu [16 × PR × 2] × RR PROGRAMMABLE WORD LENGTH • 8 bits • 9 bits (8 bits of data plus parity bit) l RECEIVER WAKE FUNCTION BY THE MOST SIGNIFICANT BIT OR IDLE LINE ST 7 PERIPHERALS 46

ST 7 SCI Overview (2) l 3 FLAGS Ø Buffer full Ø Transmit buffer empty Ø End of transmission l MUTING FUNCTIONS FOR MULTIPROCESSOR CONFIGURATIONS l NOISE, OVERRUN AND FRAME ERROR DETECTION l 4 INTERRUPT SOURCES WITH FLAGS ST 7 PERIPHERALS 47

ST 7 SCI Serial data format LSB Previous frame or idle line Start bit MSB Following frame or idle line 8 bit data Optionnal parity bit ST 7 PERIPHERALS Stop bit 48

SCI Sampling Data Format Bit Time Sampling Time l Each bit time is Received bit value 000 0 0 001 0 1 010 0 1 011 1 1 100 0 1 101 1 1 110 1 1 111 1 Ø Divided by 16 by the SCI clock Ø Sampled 3 times on the 8 th, 9 th and 10 th count of the SCI clock l NF Flag Data Sampled values 0 NF flag is set if the 3 sampling are not equal but the reception is still available ST 7 PERIPHERALS 49

SCI Block Diagram Data Register RDI pin Transmit data register Receive data register Transmit shift register Receive shift register TDO pin Transmit rate Control Transmit Control register 1 Control Register 2 Wake-Up Unit Receive Control Receive rate Control Status Register SCI Interrupt Control ST 7 PERIPHERALS fcpu /2 / 16 / PR 50

ST 7 SCI Clock selection EXTENDED PRESCALER TRANSMITTER RATE CONTROL ETPR EXTENDED TRANSMITTER PRESCALER REGISTER ERPR EXTENDED RECEIVER PRESCALER REGISTER EXTENDED PRESCALER RECEIVER RATE CONTROL EXTENDED PRESCALER f CPU TRANSMITTER CLOCK TRANSMITTER RATE CONTROL /16 /2 /PR BRR SCP 1 SCP 0 SCT 2 SCT 1 SCT 0 SCR 2 SCR 1 SCR 0 RECEIVER CLOCK RECEIVER RATE CONTROL CONVENTIONAL BAUD RATE GENERATOR ST 7 PERIPHERALS 51

SCI Configurable Baud Rate TR SCT 2: SCT 0 RR SCR 2: SCR 0 l l l PR SCP 1, SCP 0 ETPR /ERPR Baud Rate 64 - 110 13 - 11 0 300 16 - 100 13 - 11 0 1200 8 - 011 13 - 11 0 2400 4 - 010 13 - 11 0 4800 2 - 001 13 - 11 0 9600 8 - 011 3 - 01 0 10400 1 - 000 13 - 11 0 19000 X X 13 38000 Values given for f. CPU =8 MHz PR selected by SCP 1& SCP 0 bits of SCIBRR Register TR selected by SCT 2, SCT 1 & SCT 0 bits of SCIBRR Register RR selected by SCR 2, SCR 1 & SCR 0 bits of SCIBRR Register Reach the industry standard requirement ST 7 PERIPHERALS 52

SCI Configuration Example R 8 TIE TCIE M WAKE ILIE TE SCICR 1 RIE RE RWU SBK SCICR 2 SCP 1 SCP 0 SCT 2 SCT 1 SCT 0 SCR 2 SCR 1 SCR 0 SCIBRR l Fill the SCI registers in order to configure the Sci cell in Ø 8 Bit word reception at 9600 Bauds Ø 8 bit word transmission at 1200 Bauds Ø Interrupt generation when RDRF is set (reception flag) l f. CPU = 8 MHz ST 7 PERIPHERALS 53

ST 7 EEPROM Data 8 -Bit CORE SP PCL PCH Interrupt Controller INT Accu Index X Index Y CC PORT l Optional features : Ø Ø Ø 16 -bit timer Peripheral Program Peripheral ST 623 x BLOCK DIAGRAM Otp / Rom Peripheral Data Ram 256 bytes Peripheral Test/Vpp Ø EEPROM Peripheral Reset Data EEprom AD converter 16 -bit Timer 8 -bit Auto Reload Timer SPI SCI I 2 C Peripheral Ø Programmable Op. Amp Ø CAN Oscillator Power Supply Watchdog Timer Optional ST 7 PERIPHERALS 54

SPGA Software Programable Gain Amplifier 8 -Bit CORE SP PCL PCH Interrupt Controller INT Accu Index X Index Y CC PORT l Optional features : Ø Ø Ø Ø 16 -bit timer Peripheral Program Peripheral ST 623 x BLOCK DIAGRAM Otp / Rom Peripheral Data Ram 256 bytes Peripheral Test/Vpp Peripheral Reset Data EEprom Peripheral AD converter 16 -bit Timer 8 -bit Auto Reload Timer SPI SCI I 2 C EEPROM Ø Programmable Op. Amp Ø CAN Oscillator Power Supply Watchdog Timer Optional ST 7 PERIPHERALS 55

Programmable Op. Amp OVERVIEW l Integrated RAIL to RAIL Op. Amp l Internal low programmable Gain (Up to 16) l Integrated reference voltage sources, VCC dependent & independent (Band-Gap). l Op. Amp Outputs internally connected to ADC input l Interupt flag in comparator mode l Power on/off bit & active in low power modes l DAC capability with PWM/ART output ST 7 PERIPHERALS 56

SPGA Block Diagram SPGA 1 Programmable gain Op-Amp To ADC Channel 8 Reference voltages: *1. 2 V, Vcc independant *8 steps, VCC dependant Analog (Amplifier ) or digital (Comparator) output ST 7 PERIPHERALS 57

SPGA MODES (1) ST 7 PERIPHERALS 58

OPAMP MODES (2) ST 7 PERIPHERALS 59

SPGA MODES (3) ST 7 PERIPHERALS 60

ST 7 CAN 8 -Bit CORE SP PCL PCH Interrupt Controller INT Accu Index X Index Y CC PORT l Optional features : Ø Ø Ø Ø 16 -bit timer Peripheral Program Peripheral ST 623 x BLOCK DIAGRAM Otp / Rom Peripheral Data Ram 256 bytes Peripheral Test/Vpp Peripheral Reset Data EEprom Peripheral AD converter 16 -bit Timer 8 -bit Auto Reload Timer SPI SCI I 2 C EEPROM Ø Programmable Op. Amp Ø CAN Oscillator Power Supply Watchdog Timer Optional ST 7 PERIPHERALS 61