Space vs Speed Binary Adders 9 1 Space

Space vs. Speed: Binary Adders 9. 1 Space vs. Speed

Binary Adders • VHDL Adder • Carry Lookahead Adder

4 -Bit Adder C A B S 1 0 0 1 1 1 0 1 0 0 1 1 0

Adder in VHDL entity adder is port ( a: in STD_LOGIC_VECTOR (3 downto 0); b: in STD_LOGIC_VECTOR (3 downto 0); sum: out STD_LOGIC_VECTOR (3 downto 0); carry: out STD_LOGIC ); end adder;

std_logic_arith. vhd

Ai B i 00 Ci 01 10 1 11 1 Ci+1 = Ai & Bi # Ci & B i # Ci & A i

std_logic_unsigned. vhd

adder. vhd

Binary Multiplier Half Adders are Sufficient Since there is no Carry-in in addition to the two inputs to sum 2 bit by 2 bit

Binary Multiplier 4 bit by 3 bit yields 7 bit result

Binary Adders • VHLD Adder • Carry Lookahead Adder

Carry Lookahead Adder C 2 = G 1 + P 1(G 0 + P 0 C 0) = G 1 + P 1 G 0 + P 1 P 0 C 0 C 3 = G 2 + P 2(G 1 + P 1 (G 0 + P 0 C 0)) = G 2 + P 2(G 1 + P 1 G 0 + P 0 C 0) = G 2 + P 2 G 1 + P 2 P 1 G 0 + P 2 Pl. P 0 C 0 G 0 -3 = G 3 + P 3 G 2 + P 3 P 2 G 1 + P 3 P 2 Pl. G 0 P 0 -3 = P 3 P 2 Pl. P 0

Ripple Carry Adder (4 -bit)

• Typically, longest delay path through n-bit ripple carry adder is 2 n + 2 • Tends to be one of the largest delays in a typical computer design Counts as 2 gate delays 0 0 2 1 2 4 3 1 0 4

4 4 0 0 2 6 5 6 4

4 6 6 0 0 4 2 8 7 8 6

8 4 6 8 0 0 6 4 2 10 9 10 8

10 8 4 6 10 8 6 4 • 10 Gate Delays • 16 -bit Adder -- 34 Gate Delays • 64 -bit Adder -- 130 Gate Delays

Carry Lookahead Adder • Uses Propogate and Generate signals to “lookahead” for incoming carry signals • More complicated hardware configuration • Substantial decrease in gate delays

Ripple Carry PFA: Partial Full Adders Carry Lookahead

• Propagate P = A xor B If P = ‘ 1’ then the carry is “propagated” through. If P = ‘ 0’ then the carry is not “propagated” through. • Generate G = A and B If G = ‘ 1’ a carry is “generated” regardless of the carry bit.

For final carry determination, the Propagate signal is ANDed with the Carry Out and the Generate signal is ORed to the resulting signal. G P Cout Cin A B Cout S P G 0 0 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 0 1 1 0 0 0 1 1 0 0 1 1 Cin

Cin A B Cout S P G 0 0 0 0 1 1 1 1 0 1 0 1 0 0 0 1 0 1 1 0 1 0 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 Always Generate a Carry for A = 1, B =1 Propagate the Carry in

Cout

2 4 1 4 Cout 2 3

2 4 PFA For Bit # 1 1 4 2 4 Cout 2 3 4 1 2 3 2 1 2 2 3 3 2 1

Bit #2 Bit #1 2 2 4 6 1 1 4 Bit #3 Bit #4 2 2 6 6 1 4 4

Significant Delay Reduction • 4 - bit Ripple: CLA: • 16 - bit Ripple: CLA: • 64 - bit Ripple: CLA: 10 Delays 6 Delays 1 CLA level: 1*4 + 2 = 6 34 Delays 10 Delays 2 CLA levels: 2*4 + 2 = 10 130 Delays 14 Delays 3 CLA levels: 3*4 + 2 = 14 But at the expense of a significant increase in the number of gates used by the circuit