SOI SPECIFIC ANALOG TECHNIQUES FOR LOWNOISE HIGHTEMPERATURE OR
- Slides: 35
SOI SPECIFIC ANALOG TECHNIQUES FOR LOW-NOISE, HIGH-TEMPERATURE OR ULTRA-LOW POWER CIRCUITS Promoteurs: Jury: Prof. J. -P. Colinge Prof. D. Flandre Dr. J. -P. Eggermont Prof. A. Kaiser Prof. P. Sobieski (président) Prof. M. Verleysen Vincent Dessard
SOI SPECIFIC ANALOG TECHNIQUES FOR LOW-NOISE, HIGH-TEMPERATURE OR ULTRA-LOW POWER CIRCUITS Content of thesis: I) A new class of ultra-low power (ULP) analog basic blocks II) SOI n-MOSFETs low-frequency noise study III) Fully differential preamplifier for instrumentation
A new class of ULP analog basic blocks Outline of presentation: Introduction - SOI vs. Bulk technology - Why ULP ? - How to achieve ULP ? Main - New ULP principle & technological considerations - 3 ULP basic blocks and their applications Conclusions
SOI vs. Bulk technology
SOI vs. Bulk technology: CMOS Inverter case Vout 0 V N+ N+ Bulk N+ Vin 5 V P+ N+ P+ P+ Standard UCL FD-SOI process N+ P 2 P+ Well Vout N+ Vin 5 V P+ Buried oxide P-substrate leakage P 1 Well leakage current P-substrate N+ N-Well Drain leakage current 0 V SOI Vin P+ P+ Vout
Why ULP ?
Why ULP ?
How to achieve ULP ?
How to achieve ULP ? P=U. I ULP ? Dynamic range constraints Difficult to I (p. A…n. A…) U How ? (can’t obtain such current with resistor !) Use of self biased multi-threshold voltage CMOSFET basic cells
New ULP principle & technological considerations
Standard UCL SOI CMOSFETs Id-Vgs characteristics (Vbs=0 V, 20°C, Vds=1 V, W/L=1/3) ID [A] logscale 10 -5 N+ 10 -6 10 -7 P+ P 1 N+ P+ 10 -8 NP 2 N PP 1 P 10 -9 P 2 10 -10 10 -12 -2 Vth NP 2 N Vth PP 1 P 10 -11 Vgs [V] -1. 5 -1 -0. 5 More Vth without process change ? … 0 0. 5 1
More Vth without process change ? … Idea: Permute/Add/Remove channel doping by intelligent use of existing masks. n-MOSFET NP 2 N (Standard) NP 1 N NP 12 N NIN (intrinsic) N+ P 2 N+ p-MOSFET PP 1 P P+ P 1 P+ P+ P 2 P+ (Standard) N+ P 1 N+ N+ P 1+P 2 N+ N+ I (NNN) N+ PP 2 P PP 12 P PIP P+ P 1+P 2 P+ P+ I (PNP) P+
Use of self biased multi-threshold voltage CMOSFET basic cells ID [A] logscale 10 -5 10 -6 10 -7 PP 12 P PP 1 P PIP NNN NIN NP 2 N NP 1 N PP 2 P PNP 10 -8 NP 12 N 10 -9 10 -10 10 -11 10 -12 -2 Vgs [V] -1. 5 -1 -0. 5 0 0. 5 1
3 ULP basic blocks and their applications
Basic cell architecture (#1) : 20°C n- & p-MOS have: -same VGS and VBS -same I VG 0 Self biased
T° dependence: UCL FD-SOI intrinsic n & p-MOSFETs Drain current [A] (logscale) PIP NIN Ibias exponentially with T° VG 0 weakly sensitive to T° ! Gate voltage [V]
Application: voltage reference/ level shifter 0. 480 Vref = Vout (VG=0 V) Vdd NIN (20/20) VS 1 NP 1 N (20/20) VS 2 PIP (20/20) PP 1 P (20/20) [A] Consumption [V] 1. E-07 0. 478 1. E-08 0. 476 1. E-09 0. 474 0. 472 1. E-10 0. 47 Max. sensitivity 200 ppm/°C 0. 468 1. E-11 T [°C] 0. 466 50 100 150 200 250 1. E-12 300
Comparison with a standard voltage reference generator based on a bandgap cell[*]. [*] die [*]: Hiten’ 99, S. Adriaensen
Generalized basic cell (#2): (differential CMOS transconductance) VGn VGp VS VN VP VS I 0 VG 0
Application: OTA Design constraints: IBias gm DC gain: f. T : (… 40 d. B …) (… few Hz … & T° dependent)
Application: Low-frequency gm-C filter (biomedical). BP, 1 Hz: Vin + Vref + Vout f 1 Hz 1. 5 p. A Simulation
Comparison with a standard gm-C 6 th order 2. 4 Hz LP filter[*] Number of poles [*]: IEEE Trans. On Circuits & Systems-II. Dec. 2000, p 1391
Basic cell (#3): ULP Diode VD PN junction diode Standard MOS diode ID IS Problem: Large reverse leakage current for low Vth ! Solution: ULP diode … IS
Basic cell (#3): ULP Diode junction diode Basic cell (#2)
‘IS’ definition: ISn ISp
Standard MOS diode ULP MOS diode Log|ID| [A] ISn=10 -10 IS=10 -10 -7 IS=10 -11 IS 0 =1 I Sp =10 -12 -10 10 = p IS=10 -13 IS VD [V] ID VD IS 1 = I Sp -13 0 VD [V] VD ID
Basic cell (#3): ULP diode measurements Linear scale
Application: memory cell (SRAM, flip-flop) Standard SRAM principle:
Application: memory cell (SRAM, flip-flop) ID 1 Word line VDD/4 D 1 Vram ID 1 -ID 2 C
Application: SRAM Static consumption over T°: 1. E-04 Reverse ULP diode V’in > 0 -V’in /2 Id [A] logscale 1. E-05 VDD ID Vin 1. E-06 1. E-07 Id Ileak Inverter 1. E-08 250°C 200°C 1. E-09 1. E-10 0 1. E-11 150°C 1. E-12 -1 -0. 5 VDD Ileak 100°C 0 0 V 25°C ID Vin 0. 5 1 1. 5
Applications: SRAM Static consumption over T°: 10 10 10 1 Mb SRAM 2 Bulk 1 PD SOI 0 FD SOI ? -1 ULP FD SOI ? -2 50 100 150 200 250 Temperature (°C) 300 350 Standby Power (W) @ 5 V Standby Current (m. A) (64 kbits SRAM) 10 1 10 0 -1 10 10 -2 10 -3
Basic blocks summary
Basic blocks and applications summary: (#2) (#1) VDn (#3) VA VGn VG VS VS VGp VK VDp -voltage reference -current source (fct T°) - differential gm - rail-to-rail OTA - low frequency filter - charge pump - memory cell - comparator (hysteresis) Future researches… - More complete experimental circuits validation. - New applications (not only for ULP !): oscillator, DTMOS, ESD, charge pump (Rload), low level battery detector, …
Conclusions
Conclusions: - An original concept of ULP basic blocks has been presented. (patent pending) - Use of standard SOI process (only optimal use of masks). - Still working at high temperature. - Most basic analog functions can be implemented: -voltage reference -OTA -filter Few p. W at -memory cell (SRAM, …) -charge pump -comparator -… 20°C !!! - Very efficient for low-frequency fixed temperature applications (biomedical). - High temperature SRAM with low static consumption can be expected.
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