Software Defined Silicon Overview l Software Defined Silicon

Software Defined Silicon 晶片功能的軟體化

Overview l Software Defined Silicon l Break l Demo l. Q&A l 30 min 5 min 20 min 10 min

Overview

Buy a Product Best Cheaper Easy to Use (User-Friendly)

Product Development Steps Product Spec / Features System Spec Hardware Spec Mechanical Spec Software Spec Development System Integration

Product Spec / Functions Cost Price Time to the Market BOM Cost

積體電路的變革 Tube Transistor SSI MSI LSI VLSI ASIC Programmable IC ASSP Shorter Development Time & Cheaper BOM

Product Market Volume Market Niche Market Big Volume Competitive & Bloody Small Volume Less Competitive ASIC ASSP Standard Solution Glue Logic Programmable Devices Non-Standard Solutions

To Design a Product ? Glue Logic ASIC / ASSP Programmable ICs Modules Solution Boards… Time to the Market By Hardware By Software BOM Cost

ASIC / ASSP Cheaper Easier Specific By Hardware Expensive Better Performance FPGA / CPLD Expensive Complicate Flexible By Software Cheaper Performance?

ASIC / ASSP Application Specific IC Designed to Perform the Specific Function VGA Chips DVD Chips Keyboard Controller 3 G Chips Mouse IC Wi-Fi Chips Its Specific Function cannot be Changed or Programmed

Programmable ICs Programmed for Functions : Flexible PAL / GAL Programmable Array Logic Gate-Based x. ROM x Read-Only Memory Hard-Wired CPLD Complex Programmable Logic Device FPGA Field-Programmable Gate Array Functional Block u. C Micro-Controller CPU-Based

Programming a Device for a Function PAL / GAL Boolean Equation by PAL Programmer ROM Programmer CPLD JTAG Port (Joint Test Action Group) Proprietary In-Circuit Programmer FPGA JTAG Port by Proprietary In-Circuit Programmer + Proprietary Languages u. C Programmer + Languages

Example : Keyboard What Kind of Keyboard? Notebook PC Keyboard Key Pad Few Keys Only ASIC Keyboard IC u. C + GPIO Glue Logic

Medical Lab Manufacture Auto Feeding System & Monitoring System Product’s Testing Tool Non-Standard Product Non-Standard Tool Special Design Special design u. C + Glue Logic PC + Glue Logic + IO Controller Cards

Any Silicon Which Its Function Can Be Easily and Flexibly Defined by CPU-Based High-Level Languages

Software Defined Silicon Programmed by High-Level Language Flexibly Define a Silicon’s Function

Software Defined Silicon

What’s SDS? Processor Program Code

Why SDS? The Fact… Fast tune-cycles and market change “Scale” grows up exponentially How do you differentiate ? “Loading” & “risk” rises up Processor… Powerful Reliable Economic

What SDS should be? Direct & programmable I/O access Programmable timing control Highly responsive processing Independent & wide processing path Inter-connection channel Reliable & convenient development tool Is It Possible ? ?

Yes, Here is an example… 8 K OTP 64 K SRAM 400 MHz RISC Processor 8 threads per core Up to 64 I/O pins

The advanced I/O Ports are tightly coupled to the core Dedicated instructions for I/O port assignment Has the concept of timing and may be synchronized to an internal reference clock or an external input clock Timed Output Time. Stamped Input Predicated Input Clocked Port with Data ready Dedicated serialisation hardware

For “Timing” In each core, Ten 100 MHz timer public resource are available for any thread. (10 ns resolution) “Timer” may link up with any event on I/O port and inter-communication channel.

Flexible “Processing Path” Eight independent threads in one core Dedicated instruction for thread job assignment Proprietary compiler to ensure 50 ~ 100 MIPS on each thread Xlink switch are available for each thread to enable threads be parallel and/or serial chained processing

Highly Responsive

Xlink Switch for inter-connection Use “chan” to connect two “chanend” threads may be on same core, different core or different chip.

Design Flow Software design and debug flow is similar to other embedded tool chains – Focus on C/C++ Adds language support to simplify tasks relating to concurrency and real-time control – XC Complete set of tools from design capture to advanced debugging Accessible both online or on your desktop machine using downloadable tools A lot of design template are available for reference

What’s XC XC looks and feels like C Support for : u I/O with timing u Communication u Event u Multiple threads and cores

The new concept for engineers Thread may be “Software task”, “Timing I/O”, “Data processing”, “State machine” System job partition Using threads as building blocks

Example: Partitioning a UART

SDS usage Scenarios Intelligent Bridge I/O expansion or companion chip SDS based ASSP

A workable example -- Real-time Audio Filter with Ethernet AV input

Demo

Designing with SDS - 1 Toggle an LED and write a UART transmit function in XC: Focus on: • ports • timers

Designing with SDS – 1 (Cont. ) Step 1 : Define BAUD_RATE & BIT_TIME Step 2 : Declare output ports for LED & Tx. D Step 3 : Use one Timer in main() routine to flash LED & send message to UART Txd port periodically Step 4 : Use another Timer resource on transmit() routine to control bit timing on UART port

Demo System

Summary : SDS is possible indeed. Using threads as building blocks of system Pending issue u. Is it possible to achieve Gbit/sec? u. How compiler work ? u. Competitive ? u. Other ?

Q&A

Thanks You