Silicon Vertex Detector SVD for Super KEKB DEPFET
Silicon Vertex Detector (SVD) for Super KEKB DEPFET meeting at Munich 25 June 2008 Toru Tsuboyama (KEK)
Topics 1. 2. 3. 4. 5. Super KEKB and upgrade schedule History of Silicon vertex detector (SVD) in Belle SVD for the Super KEKB Optimizatin Schedule • References – General information can be found in Super KEKB home page. • http: //superb. kek. jp/ – Belle meeting Indico pages. • http: //kds. kek. jp/category. Display. py? categ. Id=65 • http: //kds. kek. jp/category. Display. py? categ. Id=204
Super KEKB
Super Belle detector (Lo. I ‘ 04) SC solenoid 1. 5 T m / KL detection 14/15 lyr. RPC+Fe g tile scintillator New readout and computing systems Cs. I(Tl) 16 X 0 g pure Cs. I (endcap) Aerogel Cherenkov counter + TOF counter g “TOP” + RICH Tracking + d. E/dx small cell + He/C 2 H 6 gremove inner lyrs. use fast gas Si vtx. det. 4 lyr. DSSD g 2 pixel/striplet lyrs. + 4 lyr. DSSD 4
KEK roadmap and KEKB upgrade • KEK roadmap. – KEKB stops at end of March 2009. • Belle should accumulate 1 ab-1 of data at Y(4 S). • Commissioning of Super KEKB is done in 2012. – The schedule is too tight. (almost un-realistic) • Preparation of detector upgrade should start in 2008. – The story already delayed for 1 year already. • Please ask detail from Yamauchi in July. • Belle will run until end of 2009 and the real upgrade would start in 2010. – Negotiation between KEK, government and Japan are in progress. – Super KEKB commissioning in 2013 at the earliest.
History • SVD 1. 0 --- 1999 May – 1999 July – 3 layer DELPHI DSSD + VA 1 (1. 4 mm, 2. 6 msec shaping ) – IP chamber radius=2. 5 cm – Died of radiation damage (No gold layer in the beam pipe) • SVD 1. 2, 1. 4 1999 September- 2002 – Readout chip VA 1’ (0. 85 mm, 2. 6 msec shaping) – Beam pipe with gold layer (10 mm) • SVD 1. 6 (2002) – IP chamber vacuum leak replaced ladders with pin holed. • SVD 2 (2003 -) – 4 layer DSSD VA 1 TA (0. 35 mm, 0. 8 msec shaping) – Has been working stably with no major problems. .
SVD for the Super KEKB • Should work at high luminosity conditions – Expected back ground hit rate ~20 times larger. – Expected trigger rate: 10 KHz at maximum luminosity. – APV 25: 0. 25 mm, 50 nsec shaping, 192 stage analog ring buffer. • 6 layers: (cm) – 1 -2 are pixels or short-strip dssds. – 3 -6 are large area DSSDs. r =150 mm 17° Two thin Aim 1 cm radius beam pipe pixel layer 6 sensor layers to make low momentum tracking Slanted layer to keep acceptance, optimize incident angle and save detector size (cm)
Collision, Trigger and Readout • Collision: occurs every 2 nsec. • Trigger latency: 3 msec. • APV 25: – – Operated at 40 MHz. Analog ring buffer: 4 msec. Readout can be done while signal sampling is done. Almost no dead time unless readout queue becomes full. Noise= (246 + 36/p. F) @50 nsec Trigger Analog output preamp • Pixel: Inverter Shaper 192 stage. Analog Pipeline (4 µsec) 128 channel Multiplexer (3 µsec) – Rolling shutter: must work, though, online/offline software become complicated. – On-chip data sparsification: No realistic model exist.
Optimization of the SVD design • Intense simulation study in progress. • Position of Layer 5 and 6 – The Ks vertex reconstruction is emphasized for important physics modes. (B Ks p 0 g, B Ks Ks Ks). – The Ks efficiency can be improved with larger radius. – The layer 5 radius should be -2 cm than the Layer 6 radius in order to maximize the physics sensitivity. • Layer 1 and 2 – To be realized with pixel sensor. – If DSSD and APV 25 are used, APV 25 chips should be put outside the acceptance to keep good vertex resolution. • Material budgets for the outer layers – “Chip on sensors” is OK. – No deterioration of vertex resolution. – Effects to tracking is not significant.
Milestones • 2008 – Demonstrate APV 25 readout chain. • Design optimization (Osaka, Niigata) • Vienna group: APV 25 front end, repeater and FADC • Cracow group: Data acquisition board (COPPER/FINNESE) – DSSD test production • 2009 – Fix the design of Silicon vertex detector including pixel.
Technology choices • IP chamber radius – We are now more conservative. Radius will be 1. 5 cm or more. • Inner layers (DSSD or pixel) – DSSD: We can survive with DSSD for the first 2 -3 years. In case pixel sensors are not ready to be installed. – Pixel sensors: • CAP: G. Varner & Hawaii. : R&D started 2003(? ) • SOI: KEK/OKI: started 2005. • DEPFET: MPI. more mature than CAP and SOI. – Pixel readout • Outer layers – ASIC • Readout with APV 25. Do we have other chips? • Readout chips on DSSD seems to be unavoidable. – DSSD • HPK stopped production. • Companies in Europe countries: Micron, Canberra, SINTEF • Asian: Kyungpook (Korea) and Tata (India) colleagues are trying to produce DSSDs.
- Slides: 11