Silicon strips readout using Deep SubMicron Technologies JeanFranois

Silicon strips readout using Deep Sub-Micron Technologies Jean-François Genat on behalf of J. David, D. Fougeron, 1 R. Hermel 1, H. Lebbolo 2, T. H. Pham 2, F. Rossel 2, A. Savoy-Navarro 2, R. Sefri, 2 S. Vilalte 2 1 LAPP Annecy, 2 LPNHE 1 Paris Work in the framework of the Si. LC (Silicon for the Linear Collider) R&D Collaboratiion and the EUDET I 3 -FP 6 Europeean Project 12 th Workshop on Electronics for LHC and Future Experiments Valencia, Sept 25 -29 th 2006

Outline • Detector data • Technologies • Front-End Electronics • 180 nm chip • 130 nm chips • Future plans J-F Genat, LECC 06, Valencia, Sept 25 -29 th 2006

Example: A Silicon strips tracker at the ILC A few 106 Silicon strips 10 - 60 cm long Thickness 200– 500 mm Strip pitch 50– 200 mm Single sided, AC or DC coupled J-F Genat, LECC 06, Valencia, Sept 25 -29 th 2006

Silicon strips data at the ILC Pulse height: Cluster centroid to get a few µm position resolution Detector pulse analog sampling Time: Two scales: Coarse : 150 -300 ns for BC identification, 80 ns sampling Shaping time of the order of the microsecond Fine: nanosecond timing for the coordinate along the strip 10 ns sampling Not to replace another layer or double sided Position estimation to a few cm using pulse reconstruction from samples Shaping time: 20 -50 ns J-F Genat, LECC 06, Valencia, Sept 25 -29 th 2006

Coordinate along the strip SPICE L =50 n. H R =5 W Ci=500 f. F Cs= 100 f. F 15 ns 120 cm V = 8 107 m/s= c/3. 7 1 ns time resolution is 6. 4 cm J-F Genat, LECC 06, Valencia, Sept 25 -29 th 2006

Measured Pulse Velocity: 5. 5 cm/ns Measured moving a laser diode along 24 cm J-F Genat, LECC 06, Valencia, Sept 25 -29 th 2006

Outline • Detector data • Technologies • Front-End Electronics • 180 nm chip • 130 nm chips • Future plans J-F Genat, LECC 06, Valencia, Sept 25 -29 th 2006

Technologies Silicon detector and VLSI technologies allow to improve detector and front-end electronics integration Front-end chips: Thinner CMOS processes 250, 180, 130, 90 nm now available Si. Ge, less 1/f noise, faster Chip thinning down to 50 mm More channels on a chip, more functionalities, less power Connectivity: On detector bump-bonding (flip-chip) 3 D Smaller pitch detectors, better position and time resolution. Less material J-F Genat, LECC 06, Valencia, Sept 25 -29 th 2006

Outline • Detector data • Technologies • Front-End Electronics • 180 nm chip • 130 nm chips • Future plans J-F Genat, LECC 06, Valencia, Sept 25 -29 th 2006

Integrated functionalities Full readout chain integration in a single chip - Preamp-shaper Trigger decision (analog sums) sparse data Sampling: Analog pipe-lines On-chip digitization Buffering and pre-processing: Centroids, Least square fits, Lossless compression and error codes - Calibration and calibration management - Power switching (ILC) Presently 128 channels (APV, SVX), 256 -1024 envisaged (Kpix) J-F Genat, LECC 06, Valencia, Sept 25 -29 th 2006

Front-End Chip Integrate 512 -1024 channels in 90 nm CMOS: Ø amplifiers: 20 -30 m. V/MIP over 30 MIP Ø shapers: - Ø sparsifier: threshold the sum of adjacent channels Ø samplers: - - slow option 500 ns – 1 ms fast option 20 -50 ns 8 -16 samples 80 ns and 10 ns sampling clocks Event buffer 16 -deep Ø ADC: 10 bits Buffering, digital pre-processing Ø Ø Calibration Power switching saves a factor 200 at more: Ø ILC timing: 1 ms: ~ 3 -6000 trains @150 -300 ns / BC 200 ms in between J-F Genat, LECC 06, Valencia, Sept 25 -29 th 2006

Foreseen Front-end architecture Channel n+1 ‘trigger’ Sparsifier S ai. Vi > th Time tag Channel n-1 reset Strip Wilkinson ADC Calibration Control reset Analog samplers, slow, fast Ch # Waveforms Preamp + Shapers Counter Charge 1 -40 MIP, Time resolution: BC tagging 150 -300 ns, Technologies: Future: J-F Genat, LECC 06, Storage Deep Sub-Micron CMOS 180 -130 nm Si. Ge &/or deeper DSM Valencia, Sept 25 -29 th 2006 fine: ~ 1 ns

Outline • Detector data • Technologies • Front-End Electronics • 180 nm chip • 130 nm chips • Future plans J-F Genat, LECC 06, Valencia, Sept 25 -29 th 2006

Silicon - Preamp - Shaper - Sample & Hold - Comparator 16 + 1 channel UMC 180 nm chip J-F Genat, LECC 06, Valencia, Sept 25 -29 th 2006 3 mm (layout and picture)

Process spreads Preamp gains statistics J-F Genat, LECC 06, Valencia, Sept 25 -29 th 2006 Process spreads: 3. 3 %

Shaper output noise 375 e- RMS 375 e- +10. 4 e-/p. F input noise with chip-on-board wiring 275 + 8. 9/p. Fsimulated J-F Genat, LECC 06, Valencia, Sept 25 -29 th 2006

Tests Conclusions 12 chips tested (’ 05) The UMC CMOS 180 nm process is mature and reliable: - Models mainly OK - Only one transistor failure over 12 chips - Process spreads of a few % Beam tests in October ’ 06 at DESY Encouraging results regarding CMOS DSM go to 130 nm J-F Genat, LECC 06, Valencia, Sept 25 -29 th 2006

Outline • Detector data • Technologies • Front-End Electronics • 180 nm chip • 130 nm chips • Future plans J-F Genat, LECC 06, Valencia, Sept 25 -29 th 2006

Front-end in CMOS 130 nm CMOS: - Smaller Faster More radiation tolerant Less power Will be (is) dominant in industry Features: - J-F Genat, LECC 06, Design more constraining Reduced voltage swing (Electric field constant) Leaks (gate/subthreshold channel) Models more complex, sometimes not accurate Valencia, Sept 25 -29 th 2006

UMC Technology parameters 180 nm • • • 3. 3 V transistors Logic supply Metals layers MIM capacitors Transistors J-F Genat, LECC 06, yes 1. 8 V 6 Al 1 f. F/mm² Three Vt options Valencia, Sept 25 -29 th 2006 130 nm yes 1. 2 V 8 Cu 1. 5 f. F/mm 2 Low leakage option

130 nm 4 -channel test chip Channel n+1 Sparsifier Can be used for a “trigger” S ai. Vi > th Time tag Channel n-1 reset Analog samplers, (slow) Wilkinson ADC Strip Ch # Preamp + Shaper DC servo implemented for DC coupled detectors UMC CMOS 130 nm Sent in May, received in August Being tested J-F Genat, LECC 06, Valencia, Sept 25 -29 th 2006 Waveforms Counter Clock 3 -96 MHz

Analog pipeline simulation J-F Genat, LECC 06, Valencia, Sept 25 -29 th 2006

Silicon 180 nm 130 nm Picture J-F Genat, LECC 06, Valencia, Sept 25 -29 th 2006

One channel chip with DC servo to accommodate DC coupled detectors Preamp Shaper DC reference To be sent this Monday J-F Genat, LECC 06, Valencia, Sept 25 -29 th 2006 Analog sampler

Some issues with 130 nm design Noise likely not properly modeled (UMC dixit, to be checked) Design rules more constraining Some design rules (via densities) not available under Cadence Calibre (Mentor) required Low Vt transistors leaky (Low leakage option available) J-F Genat, LECC 06, Valencia, Sept 25 -29 th 2006

Possible issues: noise: 130 nm vs 180 nm (simulation) PMOS: 180 nm 130 nm gm=944. 4 u. S 1 MHz 3. 508 n. V/sqrt(Hz) gm=815. 245 u. S 1 MHz 7. 16 n. V/sqrt(Hz) Thermal noise hand calculation = 3. 42 n. V/sqrt(Hz) Thermal noise hand calculation = 3. 68 n. V/sqrt(Hz) Noise measured by Wladimir Gromov (NIKHEF) with IBM 130 nm OK J-F Genat, LECC 06, Valencia, Sept 25 -29 th 2006

Transistors leaks - Gate-channel due to tunnel effect - Through channel when transistor switched-off Sub-threshold current Nano-CMOS Circuit and Physical design B. P Wong, A. Mittal, Y. Cao, G. Starr, 2005, Wiley 130 nm 180 nm Gate leakage J-F Genat, LECC 06, Valencia, Sept 25 -29 th 2006 90 nm - 180 nm OK - 130 nm, no gate leaks sub-threshold leaks - 90 nm, gate + sub-threshold leaks

Outline • Detector data • Technologies • Front-End Electronics • 180 nm chip • 130 nm chips • Future plans J-F Genat, LECC 06, Valencia, Sept 25 -29 th 2006

Planned on-chip digital Chip control Buffer memory Processing for - Calibrations - Amplitude and time least squares estimation, centroids - Raw data lossless compression Tools - Digital libraries in 130 nm CMOS available (Artisan, VST) - Place & Route tools: Cadence + design kits - Synthesis from VHDL/Verilog - Some IPs: PLLs, SRAM J-F Genat, LECC 06, Valencia, Sept 25 -29 th 2006

Next developments Implement the fast (20 -50 ns shaping) version including: - Preamp + Shaper (20 -100 ns) - Fast sampling - Power cycling Submit a full 128 channel version including slow and fast analog processing, power cycling, digital J-F Genat, LECC 06, Valencia, Sept 25 -29 th 2006

The End … J-F Genat, LECC 06, Valencia, Sept 25 -29 th 2006

backup J-F Genat, LECC 06, Valencia, Sept 25 -29 th 2006

Beam-tests at DESY October 2006 J-F Genat, LECC 06, Valencia, Sept 25 -29 th 2006

Wiring Detector to FE Chips Wire bonding Flip Chip Technology Courtesy: Marty Breidenbach (Cal Si. D) OR (later) J-F Genat, LECC 06, Valencia, Sept 25 -29 th 2006

Wiring Detector to FE Chips Courtesy: Ray Yarema, FEE 2006, Perugia J-F Genat, LECC 06, Valencia, Sept 25 -29 th 2006

3 D Wiring Courtesy: Ray Yarema, FEE 2006, Perugia J-F Genat, LECC 06, Valencia, Sept 25 -29 th 2006

Linearities (180 nm) +/-1. 5% +/-0. 5% expected +/-6% +/-1. 5% expected J-F Genat, LECC 06, Valencia, Sept 25 -29 th 2006

Noise summary (180 nm) Measured using COB test card J-F Genat, LECC 06, Valencia, Sept 25 -29 th 2006

Manuel Lozano (CNM Barcelona) Chip connection • Wire bonding – Only periphery of chip available for IO connections – Mechanical bonding of one pin at a time (sequential) – Cooling from back of chip – High inductance (~1 n. H) – Mechanical breakage risk (i. e. CMS, CDF) • Flip-chip – Whole chip area available for IO connections – Automatic alignment – One step process (parallel) – Cooling via balls (front) and back if required – Thermal matching between chip and substrate required – Low inductance (~0. 1 n. H) J-F Genat, LECC 06, Valencia, Sept 25 -29 th 2006

Manuel Lozano (CNM Barcelona) Bump bonding flip chip technology • Electrical connection of chip to substrate or chip to chip face to face flip chip • Use of small metal bumps bump bonding CNM • Process steps: J-F Genat, LECC 06, Valencia, Sept 25 -29 th 2006 – Pad metal conditioning: Under Bump Metallisation (UBM) – Bump growing in one or two of the elements – Flip chip and alignment – Reflow – Optionally underfilling

Manuel Lozano (CNM Barcelona) Bump bonding flip chip technology • Bumping technologies – Evaporation through metallic • Expensive technology mask – Especially for small quantities – Evaporation with thick (as in HEP) photoresist – Big overhead of NRE costs – Screen printing • Minimal pitch reported: 18 µm but. . . – Stud bumping (SBB) • Few commercial companies for fine – Electroplating pitch applications (< 75 µm) – Electroless plating – Conductive Polymer Bumps – Indium evaporation J-F Genat, LECC 06, Valencia, Sept 25 -29 th 2006

Noise: 130 nm vs 180 nm (simulation) NMOS : 130 nm W/L = 50 u/0. 5 u Ids=48. 0505 u, Vgs=260 m. V, Vds=1. 2 V gm=772. 031 u. S, gms=245. 341 u. S, gds=6. 3575 u. S 180 nm W/L=50 u/0. 5 u Ids=47 u. A, Vgs=300 m. V, Vds=1. 2 V gm=842. 8 u. S, gms=141. 2 u. S, gds=16. 05 u. S 1 MHz --> 24. 65 n. V/sqrt(Hz) 1 MHz --> 4 n. V/sqrt(Hz) 100 MHz --> 5 n. V/sqrt(Hz) Thermal noise hand calculation = 3. 78 n. V/sqrt(Hz) 10 MHz --> 3. 49 n. V/sqrt(Hz) Thermal noise hand calculation = 3. 62 n. V/sqrt(Hz) J-F Genat, LECC 06, Valencia, Sept 25 -29 th 2006