Si Ge Bi CMOS 65 GHz BPSK Transmitter

Si. Ge Bi. CMOS 65 -GHz BPSK Transmitter and 30 to 122 GHz LC-Varactor VCOs with up to 21% Tuning Range Chihou Lee, Terry Yao, Alain Mangan, Kenneth Yau, Miles Copeland*, Sorin Voinigescu University of Toronto - Edward S. Rogers, Sr. Dept. of Electrical & Computer Engineering * Professor Emeritus, Carleton University, Ottawa, ON, Canada.

Outline • Motivation • VCO and BPSK transmitter circuit topologies • Design methodology for lowest phase noise VCOs • Experimental results • Conclusions

Motivation • Advanced communications (60 -GHz radio) and radar systems (77 -GHz cruise control). • Investigate a systematic VCO design methodology focused on lowest phase noise.

Outline • Motivation Ø VCO and BPSK transmitter circuit topologies • Design methodology for lowest phase noise VCOs • Experimental results • Conclusions

Fundamental Mode VCO Topology • Differential Colpitts Configuration • C 2 implemented as accumulation-mode n. MOS varactor. • Cascode for improved isolation of output from resonant tank, and power gain. • LEE & Resistive tail bias with low-pass filter to reduce bias circuit’s noise contribution.

Push-Push VCO Topology • Active and passive components operate at ½ output frequency • Similar topology as fundamentalmode VCO except output is taken at Q 2 & Q 4’s base. • Intrinsically isolated output. • Allows differential tuning (VTUNE+POS, VTUNE, -NEG).

VCO Schematics 35 -GHz VCO (Fund. ) 70 -GHz VCO (Push-Push)

BPSK Transmitter Schematic

Outline • Motivation • VCO and BPSK transmitter circuit topologies Ø Design methodology for lowest phase noise VCOs • Experimental results • Conclusions

Designing for Lowest Phase Noise VCO Design Parameters: • VTANK – tank voltage swing • QTANK – tank quality factor • JBIAS – current density • C 1: C 2 – capacitance ratio • LB – base inductance • IBIAS – bias current Simulation Test Circuit

1. Optimum C 1: C 2 Ratio

2. Optimum Current Density (JBIAS) OPTIMUM JBIAS = optimum noise current density (Jopt) of cascode.

3. Optimum Bias Current (IBIAS)

3. Optimum Base Inductance (LB) Smallest LB results in Lowest Phase Noise

VCO Design Methodology 1. Maximize quality factor (Q) of resonant tank. 2. Bias transistors at optimum noise current density Jopt. Show a simulated plot of Jopt @ 40 GHz & f. T, f. MAX for cascoded transistor configuration

VCO Design Methodology (con’t) 4. Choose smallest reproducible base inductance (LB). 5. Sweep IBIAS to minimize phase noise while choosing C 1: C 2 ratio to maximize VTANK while maintaining fosc. 6. Add inductive emitter degeneration LE. 1. [Li and Rein, JSSC 2003]

VCO Design Space Examined 13 VCOs & Oscillators fabricated to examine the impact on phase noise of: 1. Base inductance (LB) 2. Accumulation-mode n. MOS varactors versus. MIM capacitors 3. Addition of LE 4. Operation on 2 nd harmonic versus. operation on fundamental.

Outline • Motivation • VCO and BPSK transmitter circuit topologies • Design methodology for lowest phase noise VCOs Ø Experimental results • Conclusions

Fabrication Technology • Jazz Semiconductor’s commercial SBC 18 0. 18 m Bi. CMOS process. • Peak f. T and f. MAX near 155 GHz. NFmin extracted from measured y-parameters [S. P. Voinigescu, et. al, JSSC 1997]

Varactor Q Characteristics

Microphotographs Family of 13 VCOs: Fundamental-Mode: (8) 35 GHz, (2) 60 GHz, Push-Push: (1) 70 GHz, (2) 120 -GHz

Microphotographs (con’t) 65 -GHz BPSK transmitter

35 -GHz VCO Measurements Averaged Spectral Plots for 35 -GHz VCO (LB = 100 p. H, with LE): (A) VCO (B) Fixed Freq. Oscillator

35 -GHz VCO Measurements (con’t) Tuning and Output Power Characteristics:

Lowest Phase Noise Design Space Impact of: 1. Base Inductance 2. Inductive Emitter Degeneration (LE)

60 -GHz VCO Measurements Averaged Spectral Plots: (A) VCO (B) Fixed Freq. Oscillator

60 -GHz VCO Measurements (con’t) Measurements over Temperature:

Push-Push VCO Measurements Spectral Plots: (a) 70 -GHz VCO (b) 120 -GHz VCO POUT > -14 d. Bm POUT > -30 d. Bm

Push-Push VCO Measurements (con’t) Tuning Characteristics:

Si-Based mm-wave VCO Comparison L{foffset} (d. Bc/Hz) Tuning Range PDC (m. W) POUT (d. Bm) FOM * f. T/f. MAX (26 -GHz) -87 at 100 KHz 15% 75 1. 0 -177. 5 ~ 40/50 GHz (BJT) (40 -GHz) -97 at 1 MHz 15% 17. 3 -5. 0 -171. 7 0. 13 m (SOI) (43 -GHz) -110 at 1 MHz 26% 280 6. 5 -184. 7 ~ 200 GHz (HBT) (77 -GHz) -95 at 1 MHz 6% 930 14. 3 -177. 3 ~ 200 GHz (HBT) (63 -GHz) pp -85 at 1 MHz 4% 119 -4. 0 -156. 2 0. 25 m CMOS (150 -GHz) pp -85 at 1 MHz 23% 170 -5. 0 -161. 2 ~ 220 GHz (HBT) 35 -GHz Osc. -112. 7 at 1 MHz N/A 193 4. 0 -184. 5 ~ 155 GHz (HBT) 35 -GHz VCO -110. 3 at 1 MHz 19% 188 4. 0 -181. 4 ~ 155 GHz (HBT) 60 -GHz Osc. -104 at 1 MHz N/A 244 4. 0 -179. 5 ~ 155 GHz (HBT) 60 -GHz VCO -103 at 1 MHz 13% 240 4. 0 -178. 6 ~ 155 GHz (HBT) 70 -GHz VCO pp -94 at 1 MHz 21% 128 > -14 < -156. 8 ~ 155 GHz (HBT) Reference VCO *FOM = L{foffset} - 20 log(fosc/foffset) + 10 log(PDC/POUT) pp = push-push VCO

BPSK Transmitter Measurements No DATA: With DATA (231 -1 PRBS):

BPSK Transmitter Meas. (con’t) With DATA (27 -1 PRBS pattern):

Outline • Motivation • VCO and BPSK transmitter circuit topologies • Design methodology for lowest phase noise VCOs • Experimental results Ø Conclusions

Conclusions • Presented, with experimental validation, a systematic VCO design methodology for lowest phase noise. • Compared to a MIM capacitor, accumulation-mode n. MOS varactors degrades phase noise by 1 -2 d. B. • Inductive degeneration lowers phase noise by 3 -4 d. B. • Operation on 2 nd harmonic increases tuning range by 50% - at expense of lower POUT • First 65 -GHz BPSK transmitter.

Acknowledgements • Jazz Semiconductor, Gennum Corporation. • Canadian Foundation for Innovation, Micronet, Canadian Microelectronics Corporation, NSERC. • Marco Racanelli and Paul Kempf.