Si Five Promotes RISCV Technology Innovation and Development

Si. Five Promotes RISC-V Technology Innovation and Development Si. Five推� RISC-V技�� 新与� 展 周杰 �昉科技�售�� jie. zhou@sifive. com Sept. 2019 CONFIDENTIAL – COPYRIGHT 2018 SIFIVE. ALL RIGHTS RESERVED.

What is RISC-V? A license-free, royalty-free High-quality, Suitable for all types of computing system, RISC ISA specification, Originally from UC Berkeley RISC-I 2 CONFIDENTIAL – COPYRIGHT 2018 SIFIVE. ALL RIGHTS RESERVED. RISC-III (aka SOAR) RISC-IV (aka SPUR) RISC-V (Raven-1, 28 nm FDSOI, 2011)

FOUNDATION David Patterson Google杰出 程师 & Si. Five 技术顾问 Andrew Waterman Si. Five 联合创始人 & 首席 程师 Yunsup Lee Si. Five 联合创始人 & CTO Krste Asanovic Si. Five 联合创始人 & 首席架构师 We invented RISC‑V Si. Five’s founders are the same UC Berkeley professor and Ph. Ds who invented and have been leading the commercial implementation of the RISC‑V Instruction Set Architecture (ISA) since 2010 CONFIDENTIAL – COPYRIGHT 2018 SIFIVE. ALL RIGHTS RESERVED. 3

RISC-V发展史及其标志性事件 Privileged Arch, v 1. 10 RISC-V Foundation Incorporated CONFIDENTIAL – COPYRIGHT 2018 SIFIVE. ALL RIGHTS RESERVED. 20 20 Red. Hat to RISC-V We are Here 1 st China 5 City Tour Qualcomm to RISC-V 1 st RISC-V Summit 19 20 20 18 WDC to RISC-V 1 st Commercial So. C Commercial Softcores 17 NVIDIA to RISC-V 20 16 15 20 14 20 13 20 12 First Linux Port 20 11 20 20 10 RISC-V ISA project begins 1 st Workshop User ISA v 1. 0, Raven-1 tapeout (28 nm) RVC MS thesis Si. Five Incorporated User ISA v 2. 0 IMAFD 20 1 st Rocket tapeout, EOS 14 45 nm 1 st Commercial Linux So. C Hot Chips 2014 4

What’s Different about RISC-V? Simple Stable • Far smaller than other commercial ISAs • Base and standard extensions are frozen • Additions via optional extensions, not new Clean-slate design • Clear separation between user and privileged ISA • Avoids µarchitecture or technologydependent features versions Community designed • Developed with leading industry/academic experts and software developers Modular ISA designed for extensibility/specialization • Small standard base ISA, with multiple standard extensions • Sparse and variable-length instruction encoding for vast 5 opcode space CONFIDENTIAL – COPYRIGHT 2018 SIFIVE. ALL RIGHTS RESERVED.

Why Si. Five? • Leaders in RISC-V Inventors of RISC-V Major contribution in most all foundation working group Leaders in RISC-V standardization Most complete product line of CPU IP: from microcontrollers, to embedded, to high-performance multi-core processors – Very easy to customize. Si. Five team has 8 years of experience taping out RISC-V silicon. . – Silicon-proven and our licensees are shipping – – Freedom Everywhere Base Platform Raven-3 Raven-1 Raven-2 Started RISC-V Project May Raven-3. 5 Apr May 2011 2010 2012 Aug Feb 2013 Started Development of RISC-V Core Generator Jul Sep Mar 2014 Nov Jul Aug 2015 2016 Nov Oct 2017 EOS 22 Foundation EOS 18 7 CONFIDENTIAL – COPYRIGHT 2018 SIFIVE. ALL RIGHTS RESERVED. EOS 14 EOS 16 EOS 20 Freedom Unleashed Base Platform

Why Si. Five? • Leaders in RISC-V Inventors of RISC-V Major contribution in most all foundation working group Leaders in RISC-V standardization Most complete product line of CPU IP: from microcontrollers, to embedded, to high-performance multi-core processors – Very easy to customize – Silicon-proven and our licensees are shipping – – 8 CONFIDENTIAL – COPYRIGHT 2018 SIFIVE. ALL RIGHTS RESERVED.

Why Si. Five? • Leaders in RISC-V Inventors of RISC-V Major contribution in most all foundation working group Leaders in RISC-V standardization Most complete product line of CPU IP: from microcontrollers, to embedded, to high-performance multi-core processors – Very easy to customize – Silicon-proven and our licensees are shipping – – 9 CONFIDENTIAL – COPYRIGHT 2018 SIFIVE. ALL RIGHTS RESERVED.

64 -bit Application Processors 64 -bit Embedded Processors Intelligent Cloud Embedding Intelligence from the Edge to the Cloud Intelligent Edge 32 -bit Embedded Processors CONFIDENTIAL – COPYRIGHT 2018 SIFIVE. ALL RIGHTS RESERVED.

Si. Five RISC-V Core IP Product Series Production Ready Features Industry leading 32 -bit and 64 -bit Embedded Cores ● ● ● High Performance Embedded Small, Efficient, Performance Coherent Multi-Core ● Data Cache or DTIM ● Optional I$ and optional ITIM ● Singe and Double Precision FPU Optional L 2 Cache Configurable Branch Prediction structures Optional User Mode ● ● Coherent Multi-Core ● Data Cache or DTIM ● Reconfigurable I$/ITIM Singe and Double ● Precision FPU Optional L 2 Cache Configurable Branch Prediction structures Optional User Mode ● Optional Harvard Pipeline CLIC with IRQ Vectoring Configurable TIMs Single Precision FPU Optional User Mode ● ● Si. Five’s Most Efficient Series ● ● ● High performance 64 -bit Application Cores ● Optimized High-Performance ● ● ● Multi-Core RISC-V Linux Coherent, ● Heterogeneous Multi. Core ● Data Cache or DTIM ● Optional I$ and optional ITIM Singe and Double Precision FPU Optional L 2 Cache Configurable Branch Prediction structures Coherent, ● Heterogeneous Multi. Core ● Data Cache or DTIM ● Reconfigurable I$/ITIM Singe and Double Precision FPU Optional L 2 Cache Configurable Branch Prediction structures Features Common to all Si. Five IP Products • • 11 Optional RISC-V Standard Extensions: M, A, C, F, and D • Configurable hardware multiplication performance Configurable number, type, and width of Ports • Configurable Platform Level Interrupt Controller (PLIC) • • CONFIDENTIAL – COPYRIGHT 2019 SIFIVE. ALL RIGHTS RESERVED. Run/Halt Debug with configurable number of breakpoints and support for JTAG and c. JTAG Configurable number of Hardware Performance Counters Optional Instruction Trace Optional ECC • • • Coherency Manager for cores configured with Data Caches Si. Five Insight Architectural Clock Gating

E 2 Series Features The Smallest, Most Efficient RISC-V MCU Family • E 2 Series core architectural overview – – • Efficient memory accesses – – • Provides hardware interrupt prioritization and nesting Only 6 cycles to execute the first instruction of IRQ Si. Five Custom Instruction Extension (SCIE) – 13 Ability to add multiple outbound Ports Optional Tightly Integrated Memory (TIM) and Optional Instruction Cache First RISC-V core with support for the RISC-V Core Local Interrupt Controller (CLIC) – – • RV 32(E)IMAFDCVN capable core 2 -3 stage, optional, Harvard Pipeline Easily add support for custom instructions CONFIDENTIAL – COPYRIGHT 2018 SIFIVE. ALL RIGHTS RESERVED.

Si. Five Core IP 3 and 5 series: 32 -bit Embedded Processors 64 -bit Application Processors The world's most deployed RISC-V processor IP Efficient Performance Coherent, Heterogenous, Multicore Hard Real-time capabilities Configurable CONFIDENTIAL – COPYRIGHT 2018 SIFIVE. ALL RIGHTS RESERVED. Efficient Mature

E 3/S 5 Overview High Performance 32 bit and 64 bit RISC-V MCUs • Flexible memory architecture – – • Multicore Support – – • – – Supports 16 local and up to 255 global interrupts E 3/S 5 with Interrupt Handlers in ITIM can enter an ISR in 10 cycles Support Vectoring for direct handler entry Does not require separate VIC Memory Protection – – 15 Pre-integrated and verified by Si. Five Supports up to 8+ cores Fast Interrupts – – • I-Cache can be reconfigured into I-Cache + ITIM DTIM for fast on Core Complex Data Access (D-Cache option also available) ECC/Parity Protection Off Core Complex memory access through Memory, System and Peripheral Ports 8 region physical memory protection Region locking CONFIDENTIAL – COPYRIGHT 2018 SIFIVE. ALL RIGHTS RESERVED. E 31 (AHB)* S 51 (AXI)** Cortex-R 5*** 28 nm Area 0. 066 m 2 0. 126 mm 2 0. 21 mm 2 Max Frequency 1. 5 GHz Typical 1. 4 GHz Efficiency 78 DMIPS/m. W 58 DMIPS/m. W 62 DMIPS/m. W *E 31 w/ AHB Ports, PLIC w/ 127 IRQ, Debug w/ 4 hw breakpoints, CLINT, area does not include RAMs **S 51 w/ AXI Ports, PLIC w/ 255 IRQ, Debug w/ 4 hw breakpoints, CLINT, area does not include RAMs ***unknown configuration: https: //developer. arm. com/products/processors/cortex-r 5

Si. Five Core IP 7 series: 32 -bit Embedded Processors The highest performance commercial RISC-V processor IP 64 -bit Application Processors Common Feature sets Hard Real-time capabilities Unprecedented scalability ~60% increase in Core. Marks/MHz* CONFIDENTIAL – COPYRIGHT 2018 SIFIVE. ALL RIGHTS RESERVED. 64 -bit Embedded Processors ~40% increase in DMIPS/MHz* 10% increase in Fmax* *Compared to Si. Five 5 series

Si. Five 7 series Features Scalable throughput provided by 8+1 cores per cluster Enhanced determinism for hard real-time constraints Tightly integrated memory for low latency access Functional safety provided by in-built fault tolerance mechanisms Configurable memory architecture for application specific tuning Cache lock capability for mission-critical computing 64 -bit addressability for real time latency sensitive applications Extensible design via custom instructions Mixed-precision arithmetic for efficient compute of ML workloads A single pre-integrated and verified deliverable In-cluster coherent combination of real-time and application processors CONFIDENTIAL – COPYRIGHT 2018 SIFIVE. ALL RIGHTS RESERVED.

Linley MPR – “Si. Five Raises RISC-V Performance” 18 CONFIDENTIAL – COPYRIGHT 2018 SIFIVE. ALL RIGHTS RESERVED.

Si. Five RISC-V Standard Core Roadmap Q 4’ 18 Q 1’ 19 Q 2’ 19 Released Std Core Q 3’ 19 Q 4’ 19 Q 1’ 20 Denotes Early Access Standard Core Release 8 Series Super Scalar 12 stage pipeline Out of Order 7 Series Dual Issue 8 stage pipeline E, S, U Cores 5 Series Single Issue 5 -6 stage pipeline Multi-Core S and U Cores U 84 High Performance Oo. O AP U 74 High Performance AP U 74 -MC Multi-Core AP S 76, E 76 High-Performance Embedded S 76 -MC, E 76 -MC Multi-Core Embedded U 77, S 77, E 77 Vector Unit U 54 -MC 4 U 54 S 51 U 52 No L 2$ 3 Series Single Issue 5 -6 stage pipeline Multi-Core E Cores E 31 2 Series E 24 E 21 E 20 Power/Area Optimized 2 -3 stage pipeline E and S Cores E 34 S 21 64 -bit MCU 19 CONFIDENTIAL – COPYRIGHT 2018 SIFIVE. ALL RIGHTS RESERVED. E 27, S 27 MCU + Vector Unit

Why Si. Five? • Leaders in RISC-V Inventors of RISC-V Major contribution in most all foundation working group Leaders in RISC-V standardization Most complete product line of CPU IP: from microcontrollers, to embedded, to high-performance multi-core processors – Very easy to customize - Si. Five Core Designer – Silicon-proven and our licensees are shipping – – 20 CONFIDENTIAL – COPYRIGHT 2018 SIFIVE. ALL RIGHTS RESERVED.

Si. Five is Your Virtual CPU Team Cloud-based Customize your own RISC-V core Unique for your application Not shared with your competitors Product Specific, Unique Requirements Features | Power | Performance | Area Web Interface Si. Five Core Design er Verilog RTL Verified, Customized RISC-V IP u. Controllers | Embedded | Linux | Multicore From the Inventors of RISC-V 21 CONFIDENTIAL – COPYRIGHT 2018 SIFIVE. ALL RIGHTS RESERVED.

NEW IP PARADIGM • Annual subscription allows a customer’s engineers to access Si. Five’s entire processor portfolio via a simple web interface • Configuring Si. Five’s processor IP is fast and easy • A configured processor is generated in the cloud and the results are delivered to the user’s Si. Five dashboard (RTL, SDK, test bench, docs) Si. Five Core. Designer • Explore Before allows engineers to analyze their configured cores in their system simulations before committing to using them • There is no processor modeling language to learn and no IP configuration tools to install • FPGA bitstreams are provided to allow SW to run on a configured processor RISC-V grants every user the right to modify their processor IP; Si. Five has made it incredibly easy to do so. CONFIDENTIAL – COPYRIGHT 2018 SIFIVE. ALL RIGHTS RESERVED. 22

IP Deliverables • Standard Core and Freedom Core Designer deliverables are the same. • Si. Five verifies your configuration in-house and delivers Verilog Si. Five RISC-V Core IP RTL deliverable: • Readable, Si. Five verified, Verilog with no restrictions – • Si. Five RISC-V Core IP FPGA deliverable: • Delivered Configured and Integrated Trial Variant FPGA evaluations are bitstreams of a configured core targeting our standard FPGA platforms – – – Bundled test bench with example tests • Trial Variant FPGA evaluations provide a useful platform for early software development and algorithm benchmarking – 23 CONFIDENTIAL – COPYRIGHT 2018 SIFIVE. ALL RIGHTS RESERVED. Digilent Arty Xilinx VC 707 Future FPGA platforms (Amazon F 1, Microsemi Polar Fire) Including a useful subsystem with peripherals like UARTs, and GPIOs

Software Development CONFIDENTIAL – COPYRIGHT 2018 SIFIVE. ALL RIGHTS RESERVED.

Si. Five Freedom Studio • Freedom Studio – – – • • • Peripheral register viewer Multicore debug support QEMU for simulation of Si. Five platforms – • 25 CONFIDENTIAL – COPYRIGHT 2018 SIFIVE. ALL RIGHTS RESERVED. Write and validate software before having access to silicon or emulation Debug probe support – – • Eclipse + CDT + GNU MCU Eclipse Bundled Toolchain and Open. OCD Binaries Example software for Si. Five platforms Open. OCD probes such as Olimex SEGGER JLINK Supports Windows, Mac, Linux

Supported Debug Transport Hardware - JTAG Probes Si. Five Hi. Five Unleashed & Hi. Five 1 (FTDI) Olimex ARM-USB-TINY Probe PC (Debug Host) Digilent Arty FPGA Debug Translator Open. OCD or Debug Translator SEGGER J-Link Probe 27 CONFIDENTIAL – COPYRIGHT 2018 SIFIVE. ALL RIGHTS RESERVED. Si. Five Hi. Five 1 rev. B (J-Link OB)

Why Si. Five? • Leaders in RISC-V Inventors of RISC-V Major contribution in most all foundation working group Leaders in RISC-V standardization Most complete product line of CPU IP: from microcontrollers, to embedded, to high-performance multi-core processors – Very easy to customize - Si. Five Core Designer – Silicon-proven and our licensees are shipping – – 28 CONFIDENTIAL – COPYRIGHT 2018 SIFIVE. ALL RIGHTS RESERVED.

Our Approach Has Produced Many World’s Firsts 与微� 合作�� 了世界首款基于云端�� 的芯片量� 世界首款基于RISC-V的SSD控制器 OTP Gb. E E 51 U 54 DDR L 2$ 1. 5+ GHz U 54 -MC Si. Five CPU 1 x E 51: 16 KB L 1 I$, 8 KB DTIM 支持 ECC 4 x U 54: 32 KB L 1 I$, 32 KB L 1 D$ 支持 ECC � 、双精度浮点支持基于directory的2 MB Banked L 2$ 及cache一致性并且支持ECC Chip. Link Serialized Chip-to-Chip Coherent Tile. Link Interconnect DDR 3/4, Gb. E, Peripherals 29 CONFIDENTIAL – COPYRIGHT 2018 SIFIVE. ALL RIGHTS RESERVED. Freedom U 540 由台�� 28 nm � 制造 “Si. Five基于RISC-V的IP只有其它竞品方案 1/3的功耗及1/3的面积, 这能给予我们所 需的灵活性以优化我们的架构来创造许 多突破性的产品。” – Jihyo Lee, FADU CEO

AMAZFIT Smart Watch 2 w/ ECG RMB 999 E 3 core inside AMAZFIT BIP Watch RMB 299 AMAZFIT Smart Watch 2 w/o ECG RMB 799 CONFIDENTIAL – COPYRIGHT 2018 SIFIVE. ALL RIGHTS RESERVED.

55 Over 50 commercial licensees worldwide 21 21 commercial licensees in China 6/10 6 of the top 10 semiconductor companies in the world have become Si. Five customers 120 Over 100 Si. Five RISC-V IP based projects in progress 65. 4 M 31 Si. Five US completes D-round’s financing and Qualcomm becomes a new investor CONFIDENTIAL – COPYRIGHT 2018 SIFIVE. ALL RIGHTS RESERVED.

Contact Us sales@sifive-china. com marketing@sifive-china. com recruitment@sifive-china. com • Best in class in RISC-V based solution with local customer support • Leader in RISC-V ecosystem development to support China semiconductor industry, growing with open-source community 周 杰 �昉科技�售�� 15381185012 jie. zhou@sifive. com CONFIDENTIAL – COPYRIGHT 2018 SIFIVE. ALL RIGHTS RESERVED. • Pioneer in cloud-based Saa. S service for custom ASICs.