Sharing the Working Experience ASIC IP AND BEYOND

職場經驗分享 Sharing the Working Experience ASIC • IP • AND BEYOND March 2005 Frank Cheng 鄭順發 International Business Operations / Field Marketing Development frankcheng@faraday-tech. com

Contents v Self Introduction v Sharing in Working Experience v Job Opportunities v Open Discussion 2

Contents v Self Introduction v Sharing in Working Experience v Job Opportunities v Open Discussion 3

Self Introduction - I v Graduated from 電子資訊研究所　- 甲組　in 1996 v Live in Hsin. Chu v Married with 2 sons v Career history v 1 st job in SRRC 同步輻射研究中心 (1996/7 -1997/7) - 1 yr v 2 nd job in ITRI’s 量測中心 (1997/7 -1999/6) - 2 yrs v 3 rd job in AMIC 聯笙電子　 (1999/6 -2000/2) -. 75 yr v 4 th job in Faraday 智原科技　 (2000/2 ~ ) - 5 yr 4

Self Introduction - II v SRRC 同步輻射研究中心 (1996/7~1997/7) v Division: 注射器組 v Maintained the Booster(加速環) 設備 v Power system v Electronic controlling system v Maintain Work Station and Setup Website v Why did I work for SRRC? ? ? v Higher salary $$$$$ v A stabile job v To be a civil servant v Why did I quit this job? ? ? v Radiation v A bit too stable ? ? $$$$$ lost ~1/3 5

Self Introduction - III v ITRI 量測中心 (1997/7 ~1999/6) v Division: 超音波部 v Digital system designer for Ultrasonic Diagnostic System v Developed the controller of whole system and system platform v Built up the FPGA design flow (Actel) and Interfaced the ASIC house. v Developed the Nebulizer（霧化器) product v Why did I work for ITRI? ? ? v Trend in biological medicinal engineering v A good opportunity because the whole division would be spun off from ITRI. v A good training environment, Graduate student alike v Why did I quit this job? ? ? v Manager did not want to spin off v Get back to IC design field 6

Self Introduction - IV v AMIC (1999/6 ~2000/2) v Division: Consumer Product v Developed the 8 bit u. P based audio decompression chip v Why did I work for AMIC? ? ? v IC design trend for acoustic recognition v Recall the IC design capability v Economic Issues v Why did I quit this job? ? ? v 主管操守有問題……. . 7

Self Introduction - V About Faraday v Core Technology Division v Responsible for MIPS-clone CPU implementation and migration in different process. v Companion IP designer v SIS – ARM Service Center v Transferring ARM’s framework of So. C technology to Faraday v Built up the ARM developing flow in Faraday v Customer service and promotion for ARM core based ASIC 8

Self Introduction - V v IP Service Development v Post-Sales for 8 bit u. P (80 xx), 32 bit processor core such as ARM core, MIPS-clone core and Companion IP v Pre-Sales for So. C based IP and Related Platform v OBD (Overseas Business Department) v Responsible for Overseas ASIC/IP project v Responsible for the development of So. Creative! Platform 9

Self Introduction - V v IBO國際營運中心 – Field Marketing Development v Research in Strategy Marketing v Come out the new product plan and then v Research in specific topic for subsidiary company v Technical supporting for Faraday’s customer in Europe, Japan and USA v So. C based ASIC project cooking v Product Promotion v Resource backup 10

Contents v Self Introduction v Sharing in Working Experience v Job Opportunities v Open Discussion 11

My Personal Opinions – I v Job Position 現在 未來 ＝ 立志：我要做RD . . 我真的是RD. . 我還是RD n 作資歷的累積　- 影響未來 n滾石不生苔 –頻換 作 n專業設計能力 RD ? Years Project Leader ? Years Project Manager CTO ? Years 12

My Personal Opinions – II v Job Position 現在 ＝ 立志：我要做RD RD 未來 我還是RD? ? FAE Promotion Marketing (Post-Sales) (Pre-Sales) Digital Design $$$$ 13

Suggestions v 肯定自我/他人 作價值 v 積極主動　 v 廣結善緣　 v 溝通能力 v 語文能力 – 作愉快，相處融洽 – 多做未必是錯，機會在將來 – 圈子很小，到處是熟人 – 各式各樣職務 – Global Company (D-Link, Ben. Q, Acer, Foxconn, TSMC, UMC, . . ) => CEO is Italian. v 國際觀 v Customer from Great China, Europe, Korea, Japan, USA v Competitor in WW v Business in WW v No Time Lag for Internal Business EUP <- TWN -> USA 01: 00 09: 00 17

Contents v Self Introduction v Sharing Working Experience v Job Opportunities v Open Discussion 18

Job Opportunities v Head Count : 2 for Field Marketing v Strategize, Conceive, Research RISC CPU and SOC Related Product Plan v Technical promotion, support on platform-based So. C design v Needed Background v Major in EE or Computer Engineering v Experience in IC/SOC Integration, IP Technology or Chip-Set Design (at least 4 years) Frank Cheng 鄭順發, 03 -5787888 ext. 8606 frankcheng@faraday-tech. com 19

Q&A Thank You! 20

Faraday: at a Glance v Spun off from UMC in 1993 v UMC owns 20%+ of Faraday v UMC & Faraday still share same chairman v Strategic IP partnership v Fabless ASIC and IP provider v Solid business model of 45% GM, 25% net, 30%+ CAGR v Diversified customers & markets v Listed in Taiwan exchange in 1999 v Today’s operation v 500+ employees worldwide, 330+ in R&D 21

Contact Faraday www. faraday-tech. com Faraday USA Faraday Netherlands Faraday Japan Faraday China Faraday Taiwan (HQ) Sunnyvale, CA TEL: +1. 408. 522. 8888 Amsterdam TEL: + 31. 23. 56. 20496 eusales@faraday-tech. com Tokyo TEL: + 81. 3. 5214. 0070 sales@faraday-tech. com Shanghai TEL: + 86. 21. 6406. 7523 sales@faraday-tech. com. cn Hsinchu & Taipei TEL: + 886. 3. 5787888 sales@faraday-tech. com 22

Financial Achievements 2004 revenue: $155 M 35%+ CAGR since ‘ 97 110. 8 Million USD Million NTD CAGR = 37. 68% 23

Faraday Offers ASIC Design Services, So. C Design Services, Proven IP Solutions IP Libraries / Memories ASIC Front-End ASIC Back-End Architecture Specifications Mask Tooling Behavior Modeling Wafer Manufacturing Services RTL Code Generation Microprocessors Synthesis Gate Level Verification Digital / Analog Circuit Probing & Final Testing Test Pattern Generation Physical Implementation Platform IC Packaging Services Post Layout Verification Reliability Test Services Product Engineering System-on-a-Chip 24

ASIC Infrastructure & Expertise v More than 100 people in ASIC Technology v ASIC implementation, testing, yield, and FA (70) v Design methodology & integration (35) v Production planning, logistic, and quality (25) v 10 years of experience on average v More than $50 M invested in infrastructure v e. RD, ERP, Testers, ESD machine, die/wafer bank v Complete integration of R&D, FIN, customer project, and production shipment v More than 200 project tape-outs in ’ 04 alone v 40% test chips v 10% in 0. 13 um, including four customer ASICs 25

2003 Sales Breakdown (2 -1) By application PS: Ex-IP sales revenue 26

2003 Sales Breakdown (2 -2) By customer type By geography 27

Technology Roadmaps ASIC • IP • AND BEYOND

Cell Library Roadmap ＊ 65 nm SP ＊ ＊ 90 nm LL-Rvt / Low-K 90 nm ＊ ＊ 90 nm SP-Rvt / Low-K ＊ ＊ 90 nm LL-Hvt / Low-K ＊ 130 nm 0. 15µm 130 nm L 130 E SP / FSG 0. 15µm SP＊ 2004 -07 10 ＊ 2005 -01 4 7 10 2006 -01 Legend Description：Rvt： Regular Threshold Voltage Hvt： High Threshold Voltage SP ： Standard Performance LL ： Low Leakage 4 7 10 2007 -01 Note: The right edge of each block denotes the IP’s formal release date. For more details, please visit our website at: www. faraday-tech. com 29

Memory Compiler Roadmap 65 nm SP＊ 65 nm ＊ ＊ 90 nm LL-Rvt / Low-K ＊ 90 nm SP-Svt / FSG 90 nm ＊ 90 nm SP-Svt / Low-K ＊ ＊ 90 nm SP-Hvt / Low-K ＊ 130 nm 130 m L 130 E HS / FSG 130 nm L 130 E Fusion / FSG ＊ 130 nm L 130 E SP / FSG ＊ 130 nm L 130 E LL / FSG 0. 15µm SP＊ 2004 -07 10 ＊ 2005 -01 4 7 10 2006 -01 Legend Description：Rvt：Regular Threshold Voltage HS： High Speed Hvt：High Threshold Voltage SP ：Standard Performance LL：Low Leakage 4 7 10 2007 -01 Note: The right edge of each block denotes the IP’s formal release date. For more details, please visit our website at: www. faraday-tech. com 30

Analog Essential IP Roadmap ＊ 90 nm. SP / FSG 1 GHz PLL ＊ 130 nm HS / FSG 400 MHz PLL 90 nm ＊ 90 nm SP / FSG 2 GHz PLL 130 nm ＊/ FSG 1 GHz PLL 130 nm HS ＊ ＊ PLL REG POR / BG 0. 18µm 130 nm HS / FSG Mini. PLL 0. 18µm GII Mini. PLL 0. 18µm REG 0. 18µm GII POR 0. 15µm REG 130 nm BG 0. 25µm 90 nm REG 130 nm REG 0. 15µm POR 90 nm BG 90 nm SP / FSG 800 Mb/s DLL 130 nm HS / FSG 533 Mb/s DLL ＊ 0. 35µm ＊ ＊ DLL 0. 15µm 130 nm HS / FSG 1. 6 GHz PLL 0. 15µm 1. 5 V 300 MHz PLL ＊ 130 nm HS / FSG 400 Mb/s DLL 130 nm HS / FSG Wide Range DLL 0. 15µm 1. 5 V 400 Mb/s DLL PWM RC-OSC VDT 0. 18µm GII > 50 m. A PWM 0. 18µm GII RC-OSC 10 90 nm SP PWM ＊ 130 nm HS VDT 0. 18µm GII VDT 2004 -07 ＊ ＊ 130 nm HS > 50 m. A PWM ＊ 130 nm RC-OSC 90 nm SP / FSG RC-OSC 2005 -01 ＊ 4 7 90 nm VDT 10 2006 -01 4 2006 -07 10 2007 -01 Note: The right edge of each block Legend Description：HS： High Speed denotes the IP’s formal release date. For SP ： Standard Performance more details, please visit our website at: www. faraday-tech. com 31

Analog Data Conversion & Serial Link IP Roadmaps 130 nm 10 -bit 80 MHz ADC 130 nm 8 -bit 125 MHz ADC 90 nm 0. 25µm 6 -bit 44 MHz ADC 130 nm 0. 18µm 10 -bit 80 MHz ADC 0. 15µm 130 nm 12 -bit 100 MSPS DAC 3 -channel DAC 0. 18µm 8 -bit 44 MSPS DAC 0. 18µm 0. 25µm 10 -bit 150 MSPS 3 -channel DAC 0. 25µm 0. 18µm 10 -bit 150 MSPS 3 -channel DAC 0. 35µm 130 nm 10 -bit 150 MSPS 3 -chanel DAC 0. 25µm 16 -bit Audio Codec Sigma-Delta Codec 0. 25µm 18 -bit Audio Codec 0. 18µm 16 -bit Audio Codec 130 nm 16 -bit Audio Codec RSDS TX 0. 35µm RSDS 0. 25µm RSDS 130 nm LVDS 0. 18µm LVDS TX / RX 0. 35µm LVDS 2004 -07 10 0. 25µm LVDS 2005 -01 4 0. 25µm mini LVDS 7 10 0. 18µm 1. 8 V LVDS 2006 -01 4 7 10 2007 -01 Note: The right edge of each block denotes the IP’s formal release date. For more details, please visit our website at: www. faraday-tech. com 32

USB IP Roadmap 90 nm 130 nm USB 2. 0 OTG PIE USB 2. 0 2 -port PHY USB 2. 0 Device PHY USB 2. 0 OTG PHY 0. 15µm FPGA USB 2. 0 Host PIE FUSBH 200 0. 18µm 0. 25µm FPGA USB 2. 0 2 -port Host PIE FUSBH 210 0. 35µm FPGA USB 2. 0 OTG PIE FOTG 200 FPGA 130 nm USB 2. 0 2 -port PHY 0. 18µm USB 2. 0 Device PHY v 36 0. 25µm USB 2. 0 OTG PHY 90 nm USB 2. 0 OTG PHY 130 nm USB 2. 0 OTG PHY SP＊ 130 nm USB 2. 0 OTG PHY HS＊ ＊ USB 2. 0 Host PIE Legend Description： HS：High Speed SP：Standard Performance Note: The right edge of each block denotes the IP’s formal release date. For more details, please visit our website at: www. faraday-tech. com 33

Serial-ATA IP Roadmap 90 nm 130 nm 0. 15µm Serial-ATA PHY 0. 18µm 130 nm 3 Gbps SATA PHY 0. 25µm 130 nm Multi-Port SATA PHY 0. 35µm FPGA Serial-ATA Controller With AHB I/F Note: The right edge of each block denotes the IP’s formal release date. For more details, please visit our website at: www. faraday-tech. com 34

PCI Express IP Roadmap 90 nm PCI Express PHY 130 nm 0. 18µm Single lane PHY x 1 lane 0. 15µm 0. 18µm 130 nm Single-lane PHY x 1 lane 0. 25µm 0. 35µm FPGA 130 nm Multi-lane PHY x 4 lane PCI Express Controller FPGA PCI-Express Controller End-point (PIPE) Note: The right edge of each block denotes the IP’s formal release date. For more details, please visit our website at: www. faraday-tech. com 35

Ethernet Roadmap 90 nm 10/100 Ethernet PHY 0. 25µm 10/100 Ethernet PHY 130 nm 0. 15µm 0. 18µm 10/100 4 - port Ethernet PHY 0. 18µm 0. 25µm ＊ 130 nm HS 10/100 Ethernet PHY ＊ 0. 35µm Note: The right edge of each block Legend Description：HS：High Speed denotes the IP’s formal release date. For more details, please visit our website at: www. faraday-tech. com 36

Digital IP Roadmap Wireless LAN 802. 11 a / b / g MAC / BBP Communication 10 / 100 MAC Gigabit MAC DES / 3 DES Security Engine Multimedia MPEG 4 Encoder / Decoder TV Encoder LCD Controller Peripheral MS Pro Card Controller DDRII Controller DDRI Controller 2003 -01 4 7 10 2004 -01 4 7 10 2005 -01 Note: The right edge of each block denotes the IP’s formal release date. For more details, please visit our website at: www. faraday-tech. com 37

Faraday CPU Roadmap 90 nm Clock (MHz) 130 nm ＊ 800 90 nm HS FA 626 0. 15µm 0. 18µm 0. 25µm 500 0. 35µm ＊ 130 nm HS FA 626 FPGA 400 300 ＊ 130 nm HS FA 526 HS ＊ 130 nm LL FA 526 L 130 nm FA 501 200 0. 18µm FA 526 0. 18µm FA 510 ＊ Legend Description：HS：High Speed LL：Low Leakage Note: Left and right edges indicate Tape out and Silicon proven schedule respectively. For more details please visit our website at: www. faraday-tech. com 38

Faraday Star. Cell™ IP Faraday provides a comprehensive portfolio of Peripheral IPs , as the following list , which are available right now： v DMA Controller v Static Memory Controller v SDRAM Controller v UART v Timer v Watchdog Timer v Real Time Clock v Interrupt Controller v SD Host Controller v KBD / Mouse Controller v Synchronous Serial Port v Fast Ir. DA Controller v CF Host Controller v Memory Stick Host Controller v GPIO v 10 / 100 M Ethernet MAC / PHY v PCI 33 / 66 v USB 1. 1 Device Controller / PHY v USB 2. 0 Device Controller / PHY v Smart Media Host Controller v USB 1. 1 FS / LS OTG v DDR Memory Controller v LCD Controller v TV Encoder 39

DSP Roadmap 90 nm 130 nm Fusion FD 216 130 nm Fusion FD 230 -24 130 nm 0. 15µm 0. 18µm 0. 25µm 0. 35µm FPGA 0. 18µm FD 216_HA 0 A Hardcore (w/ mailbox) 0. 18µm Co-Processor 0. 25µm FD 216_H 90 A Hardcore 2004 -7 10 2005 -01 4 7 10 2006 -01 4 7 10 2007 -01 Note: The right edge of each block denotes the IP’s formal release date. For more details, please visit our website at: www. faraday-tech. com 40

Networking Platform Roadmap Net. Composer-I: • 500 MHz 32 -bit CPU (FA 626, 130 nm, 1. 08 V, 125°C) • GMAC (*2) • Switch Fabric • Coherence Engine • MPCA (Customer Engine) • PCI-X 133 MHz • DDR-333 Controller Net. Composer-II: • 600 MHz 32 -bit CPU (FA 626, 130 nm, 1. 08 V, 125°C) • 8 Programmable Serdes • GMAC (*2) • Switch Fabric • Coherence Engine • MPCA (Customer Engine) • PCI-X 133 MHz • DDR-400 Controller with ECC Net. Composer-II (NC-II) Net. Composer-I (NC-I) 2004 Q 4 2005 Q 1 Q 2 Q 3 Q 4 2006 Note: The right edge of each block denotes the IP’s formal release date. For more details, please visit our website at: www. faraday-tech. com 41

Multimedia Platform Roadmap FIE 8150: • FA 526 Cache 16 K/16 K • MPEG 4 Codec CIF~D 1 @ 30 fps • JPEG standard Codec • TFT LCD, PCI, USB 2. 0 OTG, IDE • 10/100 Ethernet • WLAN 802. 11 a/b/g • 300 K MPCA (Metal Programmable Cell Array) FIE 8100: • FA 526 Cache 16 K/16 K • MPEG 4 Codec CIF~D 1 @ 36 fps • JPEG standard Codec • USB 2. 0 Device • TFT LCD controller • TV encoder FIE 8200: • FA 526 Cache 16 K/16 K • MPEG 4 Codec CIF~D 1 @ 30 fps • JPEG standard Codec • ISP, 2 D/3 D Graphic Engine • 300 K MPCA (Metal Programmable Cell Array) FIE 8200 FIE 8150 FIE 8100 Q 3 Q 4 2005 Q 1 Q 2 Q 3 Q 4 Note: The right edge of each block denotes the IP’s formal release date. For more details, please visit our website at: www. faraday-tech. com 42

IA Platform Roadmap UWB Wireless USB FIE 7200 • 0. 13µm process • UWB MAC+BBP+RF WLAN + Vo. IP Wi-Fi Phone Ultra Low Power Wi-Fi Phone FIE 7100 • 0. 13µm process • FA 501, USB OTG • WLAN 802. 11 g, • Audio/Video Codec, • LCD controller, TV encoder • 0. 18µm process • FA 526, FD 230 -16 • WLAN 802. 11 g, • LCD controller USB OTG PAP Ultra Low Power PAP FIE 7000 Q 1 FIE 7010 • 0. 13µm process • FA 501, USB OTG • 20 -bit Audio DAC, • LCD controller, • TV encoder, IDE/CFII • 0. 18µm process • FA 526, USB OTG • Audio Codec, • LCD controller, • IDE/CFII 2005 FIE 7110 Q 2 Q 3 Q 4 2006 Q 1 Note: The right edge of each block denotes the IP’s formal release date. For more details, please visit our website at: www. faraday-tech. com 43

Structured ASIC Family Roadmap ＊ ＊ 90 nm SP-Hvt MPCA Library 90 nm ＊ ＊ ＊ 90 nm SP-Hvt MPIO 130 nm ＊ ＊ HS MPCA 130 nm ＊ 90 nm LL-Hvt MPIO 0. 18µm 130 nm ＊ ＊ LL MPIO 130 nm ＊ MPCA LL 130 nm TEMPLATE MP-Ware 130 nm ＊ SP MPIO 0. 15µm＊ SP MPCA 0. 15µm ＊ ＊ SP MPIO 0. 18µm ＊ GII MPCA 0. 18µm＊ ＊ LL MPCA 130 nm 0. 15µm 0. 35µm 130 nm TEMPLATE Producer II 130 nm TEMPLATE FIT 9500 130 nm TEMPLATE FIT 9600 ＊ 0. 18µm ＊ 90 nm 130 nm ＊ HS MPIO＊ 130 nm ＊ ＊ SP MPCA 0. 15µm ＊ ＊ 90 nm LL-Hvt MPCA Library FPGA 130 nm TEMPLATE FIT 9700 130 nm TEMPLATE FIT 9800 0. 18µm ＊ GII MPIO 0. 25/0. 22µm ＊ MPIO 2004 -07 10 2005 -01 4 7 10 ＊ Legend Description: Hvt： High Threshold Voltage 2006 -01 SP ： Standard Performance LL ：Low Leakage MPCA：Metal Programmable Cell Array MPIO：Metal Programmable IO HS：High Speed 4 7 10 2007 -01 Note: The right edge of each block denotes the IP’s formal release date. For more details, please visit our website at: www. faraday-tech. com 44

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