Serial Interfaces SCI SPI HCS 12 Technical Training

Serial Interfaces SCI & SPI HCS 12 Technical Training, Rev 2. 0 Module 7 - SCI, Slide 1 MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.

Serial Ports • Two Asynchronous Serial Communications Interfaces (SCI) • Up to three Synchronous Serial Peripheral Interfaces (SPI) ATD 1 ATD 0 12 K SRAM 256 K FLASEEPROM SCI 1 SCI 0 Internal Bus SPI 2 SPI 1 or or PWM PWM SPI 0 8 CH CH CHAN 4 -7 0 -3 BKP INT MMI HCS 12 CPU SIM CM BDM MEBI PIM PLL ms. CAN 4 or IIC ms. CAN 3 ms. CAN 2 ms. CAN 1 BDLC or ms. CAN 0 4 K BYTES EEPROM PIT ECT 8 CHAN HCS 12 Technical Training, Rev 2. 0 Module 7 - SCI, Slide 2 MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.

HCS 12 Serial Interface Features • 2 SCI Interfaces • Up to 3 SPI interfaces • SCI is Asynchronous Communication Port SCI 0 SCI 1 Rx. D 0 Tx. D 0 SPI 0 MISO MOSI SCK SS SPI 1 MISO MOSI SCK SS SPI 2 MISO MOSI SCK SS • SCI & SPI are similar to MC 68 HC 11 with enhancements • pins may be configured as general purpose I/O • Loop mode operation for debugging • SCI & SPI have single-wire function Rx. D Tx. D 0 • SPI is a Synchronous High Speed Communication Port • Modular Architecture allows future expansion Rx. D 0 D D R S P O R T S HCS 12 Technical Training, Rev 2. 0 Module 7 - SCI, Slide 3 MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.

Serial Communications Interface (SCI) Features: • 2 SCI Interfaces • Selectable Baud Rates derived from system clock. • Advanced data sampling technique. • Standard NRZ (mark/space) data format. • Full duplexed operation. • Programmable word length ( 8 or 9 bits ). • Parity generation and checking. • Communication may be interrupt driven. HCS 12 Technical Training, Rev 2. 0 Module 7 - SCI, Slide 4 MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.

SCI Features (Cont’d) Receiver: • Receiver DATA Register FULL FLAG • ERROR DETECT FLAGS – FRAMING – NOISE – OVERRUN -- PARITY • IDLE LINE DETECT FLAG • Receiver WAKE-UP FUNCTION (IDLE OR ADDRESS BIT) Transmitter: • TRANSMIT DATA Register EMPTY FLAG • TRANSMIT COMPLETE FLAG • PARITY GENERATION • BREAK SEND HCS 12 Technical Training, Rev 2. 0 Module 7 - SCI, Slide 5 MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.

SCI Block Diagram HCS 12 Technical Training, Rev 2. 0 Module 7 - SCI, Slide 6 MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.

Double Buffering Transmitter: Receiver: DATA IN P A R I T Y T 8 G E N. DATA IN TDR BUFFER SHIFT REGISTER DATA OUT SHIFT REGISTER R 8 RDR BUFFER DATA OUT • TDRE Flag sets each time new data is transferred from the TDR Buffer to the transmit serial shift register. • RDRF Flag sets each time new data is transferred from the serial shift register to the RDR Buffer. • TC - Transmission Complete Flag . • IDLE - Idle Interrupt Flag HCS 12 Technical Training, Rev 2. 0 Module 7 - SCI, Slide 7 MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001. P A R I T Y C H E C K

SCI Data Format SINGLE FRAMES: (9 BIT DATA SHOWN AS EXAMPLE) 0 1 2 3 4 5 6 7 8 0 1 2 3 4 IDLE LINE • • • S LS Bit T A R T S MS Bit T O P st 1 FRAME S T A R T nd 2 FRAME • LEAST SIGNIFIGENT BIT IS TRANSMITTED FIRST ENTIRE MESSAGE: (3 FRAMES SHOWN AS EXAMPLE) 0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 IDLE LINE 7 8 IDLE LINE S T A R T st 1 FRAME S T O P S T A R T nd 2 FRAME S T O P S T A R T rd 3 FRAME • TRANSMISSION IS COMPLETE ONCE THIRD FRAME HAS BEEN TRANSMITTED. HCS 12 Technical Training, Rev 2. 0 Module 7 - SCI, Slide 8 MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001. S T O P

SCI Registers (1 of 4) SCIBH/L - SCI Baud Rate Control Register Address offset $0000 $0001 Reserved SCI BAUD RATE FORMULA SCIBaud Rate = E CLK 16 x BR FOR 9600 BAUDRATE BR = 16 MHZ/(16 * 9600) = 104 Where BR is the contents of the Baud Register {1, 2, 3, . . . . , 8191}. Note - Baud Rate Generator is Disabled until the Transmitter or Receiver is Enabled for first time after reset. Also Disabled when = 0. BTST, BSPL & BRLD BITS ARE USED FOR TESTING. HCS 12 Technical Training, Rev 2. 0 Module 7 - SCI, Slide 9 MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.

SCI Registers (2 of 4) SCCR 1 - SCI Control Register 1 Address Offset $0002 1 = EVEN PARITY 0 = ODD PARITY 1 = PARITY Enabled 0 = PARITY Disabled SCISWAI - SCI Stop in Wait mode 0 = Normal operation 1 = SCI Disabled in Wait mode 1 = NORMAL IDLE TIME 0 = SHORT IDLE TIME 1 = IDLE LINE WAKE-UP 0 = ADDRESS MARK WAKE-UP 1 = 9 -BIT DATA 0 = 8 -BIT DATA LOOP MODE FUNCTIONS LOOPS 0 RSRC x Function Normal Operation 1 0 Loop mode with Rx internally connected to Tx 1 1 Single-wire mode with Rx input connected to Tx HCS 12 Technical Training, Rev 2. 0 Module 7 - SCI, Slide 10 MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.

SCI Modes LOOPS = 1, RSRC = 0 LOOP MODE ( Tx. D OUTPUT) LOOP MODE ( NO Tx. D OUTPUT) SCI Receiver RECEIVE WOMS TXDDR = 0 Tx. D Transmitter Receiver SCI TRANSMIT Rx. D WOMS TXDDR = 1 TXDDR = 0 SINGLE WIRE MODE SCI Transmitter Tx. D WOMS SCI Receiver RECEIVE LOOPS = 1, RSRC = 1 SCI Tx. D Transmitter Receiver Rx. D TRANSMIT TXDDR = 1 GPIO STATION #1 Rx. D GPIO SINGLE WIRE MODE SCI Rx. D GPIO STATION #2 STATION #3 TX RX SINGLE-WIRE COMMUNICATIONS HCS 12 Technical Training, Rev 2. 0 Module 7 - SCI, Slide 11 MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.

SCI Register (3 of 4) SCICR 2 - SCI Control Register 2 Address offset $00 C 3 TIE - Transmitter Interrupt Enable 1 = Transmitter IRQ Enabled 0 = Transmitter IRQ Disabled ILIE - Idle Line Interrupt Enable 1 = IDLE IRQ Enabled 0 = IDLE IRQ Disabled TCIE - Transmit Complete Interrupt Enable 1 = Transmitter Complete IRQ Enabled 0 = Transmitter Complete IRQ Disabled TE _ Transmitter Enable 1 = Transmitter Enabled 0 = Transmitter Disabled RIE - Receiver Interrupt Enable 1 = Receiver IRQ Enabled 0 = Receiver IRQ Disabled Receiver Enable 1 = Receiver Enabled 0 = Receiver Disabled SCISR 1 RWU - Receiver Wake-up 1 = Enter Receiver Wake-UP 0 = Exit Receiver Wake-UP SBK - Send Break 1 = Send Break 0 = Terminate Break - SCI Status Register 1 Address offset $00 C 4 HCS 12 Technical Training, Rev 2. 0 Module 7 - SCI, Slide 12 MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.

Receiver, Data Bit Sampling DATA BIT SAMPLE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 NEXT BIT PREVIOUS BIT • BIT LOGICAL VALUE IS THE VALUE OF 2 OUT OF THE 3 SAMPLES • IF ALL THREE SAMPLES DO NOT AGREE, THEN THE NOISE FLAG IS SET • RECEIVE SAMPLE CLOCK = 16 x BAUD RATE. HCS 12 Technical Training, Rev 2. 0 Module 7 - SCI, Slide 13 MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.

SCI Registers (4 of 4) SCISR 2 - SCI Status Register 2 Address offset $0005 BRK 13 - Break Transmit Character Length 0 = Break Char is 10 or 11 bits long 1 = Break Char is 13 or 14 bit long SCIDRH/L TXDIR - Transmitter pin direction 0 = Tx. D pin is input in Single-Wire mode 1 = Tx. D pin is output in Single-Wire mode RAF - Receiver Active Status 1 = Receiver Active 0 = Receiver not Active - SCI Data Register High/Low Address offset $0006 Address offset $0007 Note: R 8 and T 8 are used when 9 -bit char is required HCS 12 Technical Training, Rev 2. 0 Module 7 - SCI, Slide 14 MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.

SCI Initialization 1. SELECT BAUD RATE WRITE TO BAUD Register (SCP 0 -1, SCR 0 -2) 2. SELECT WORD LENGTH AND WAKEUP WRITE SCCR 1 (M, WAKE) 3. ENABLE INTERRUPTS, TRANSMIT, RECEIVE AND WAKEUP (AS REQUIRED) WRITE TO SCCR 2 (TIE, TCIE, RIE, ILIE, TE, RWU) INTERRUPTS ENABLES FLAGS TRANSMIT DATA REG EMPTY TIE TDRE RECEIVE DATA REG FULL RIE RDRF, OR TRANSMIT COMPLETE TCIE TC IDLE LINE ILIE IDLE HCS 12 Technical Training, Rev 2. 0 Module 7 - SCI, Slide 15 MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.

SCI CONFIG & SERVICE ROUTINE Write a routine that configures and provides service for reception and transmission. The SCI is connected to a modem operating at 9600 baud, 8 data bits- no parity. use polling; none-interrupt driven routine. assume system clock frequency of 25 mhz. ORG $1000 Program begins here 1. Init Baud rate to 9600 baud. 2. Configure SCI to loop mode, with TX output 3. Configure PORTS for Tx. D 4. Set X pointer to beginning of message 5. Wait for transmitter empty status. 6. Get next char. 7. Compare pointer to end of table. 8. If not done, go get next character. 9. Else return from subroutine. Message Eof FCC FCB ‘ your name’ $0 d, $0 a $01 HCS 12 Technical Training, Rev 2. 0 Module 7 - SCI, Slide 16 MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.

IDLE Line Wakeup END WAIT FOR LINE TO GO IDLE RWU SET START N WANT ANOTHER MESSAGE ? Y RWU CLEARED WAIT FOR CHAR GOES FROM SHIFT REG TO BUFFER; RDRF IS SET N SCI OPERATION READ MESSAGE Y MESSAGE FOR THIS PORT? PROGRAM FLOW • Wake bit = 0 in SC 0 CR 2 HCS 12 Technical Training, Rev 2. 0 Module 7 - SCI, Slide 17 MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.

Address Mark Wakeup END WAIT FOR CHAR WITH MSB=1 RWU SET START RWU CLEARED N WANT ANOTHER MESSAGE ? Y CHAR GOES FROM SHIFT REG TO BUFFER; RDRF IS SET N READ MESSAGE Y MESSAGE FOR THIS PORT? PROGRAM FLOW SCI HARDWARE OPERATION • Wake bit = 1 in SCx. CR 2 HCS 12 Technical Training, Rev 2. 0 Module 7 - SCI, Slide 18 MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.

Multi-Drop Mode Receive Wakeup Operation HCS 12 Tx. D/Rx. D - - - IDLE LINE WAKEUP MESG_1 Idle Address IDLE MESG_2 Length Message 1 CRC Idle Address Length Message. . . ADDRESS MARK WAKEUP MESG_2 MESG_1 Address Length Message_1 CRC Address Length HCS 12 Technical Training, Rev 2. 0 Module 7 - SCI, Slide 19 MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001. Message_2. . .

Serial Peripheral Interface (SPI) Features: • Up to 3 High speed synchronous serial interface. • SPI 1 and SPI 2 are multiplexed with PWM Module • Primarily intended for on-board communication. • May be used for multi-processor communication. • Flexible clock format. • Full Duplexed operation. • MSB or LSB first. • Communication may be interrupt driven. HCS 12 Technical Training, Rev 2. 0 Module 7 - SCI, Slide 20 MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.

SPI, Description CPU Writes MOSI Transmit Buffer MISO SHIFT REG SCK RECEIVE REG SS SS RECEIVE REG SLAVE MASTER CPU Reads • Master initiates transfer • Master drives serial data clock to synchronize transfer • SPI receiver is double buffered HCS 12 Technical Training, Rev 2. 0 Module 7 - SCI, Slide 21 MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.

SPI, System MASTER SLAVE MISO MOSI SCK SS ENABLE DEVICE MODE MASTER SLAVE ENABLE SIGNALS MISO ENABLE MOSI SCK SS INPUT OUTPUT INPUT MISO output is Three-Stated until Enabled BY SS HCS 12 Technical Training, Rev 2. 0 Module 7 - SCI, Slide 22 MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.

Serial Peripheral Interface Useful for: 1. Communicating with simple peripherals such as LCD Drivers, A/D Converters, etc. 2. Communicating with other MCU's (eg HC 11's, MC 68 hc 16's, 6833 x’s, 6805, and MC 68 HC 08 family). (One master and multiple slaves). Description: A master and a slave device communicate by shifting bits to each other's registers. upon completion of 8 bit shifts, the following occurs: 1. A Status flag, SPIF, is set 2. An interrupt is asserted, if enabled HCS 12 Technical Training, Rev 2. 0 Module 7 - SCI, Slide 23 MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.

SPI Registers (1 of 3) SPIBR - SPI BAUD RATE Register Address offset $0002 SPPR[2: 0] - SPI Baud Rate Preselection SPR[2: 0] - SPI Baud Rate Selection Baud Rate selection may be in the range of 12. 5 MHZ down to 12. 19 KHZ. Refer to user’s manual for baud rate selection. SPIDR Address offset $0005 - SPI Data Register Note: The user should not write this register unless SPI Transmit Empty Flag is set. HCS 12 Technical Training, Rev 2. 0 Module 7 - SCI, Slide 24 MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.

SPI Register (2 of 3) SPICR 1 - SPI Control Register 1 Address offset $0000 1 = SPI IS MASTER 0 = SPI IS SLAVE 1 = SPI LSB FIRST 0 = SPI MSB FIRST 1 = SPI Transmit Interrupt Enable 0 = SPI Transmit Interrupt Disabled 1 = SPI SYSTEM Enabled 0 = SPI SYSTEM Disabled 1 = SPI Interrupt Enabled 0 = SPI Interrupt Disabled SPISR DDRS 7 SSOE 0 0 0 1 1 1 0 1 MASTER MODE SS INPUT (MODF Enabled) GP INPUT GP OUTPUT SS OUTPUT SLAVE MODE SS INPUT - SPI Status Register Address offset $0003 SPRF - SPI Receive Interrupt Flag 1 = New is received into SPIDR SPTEF - SPI Transmit Empty Interrupt Flag MODF - Mode Fault Flag 1 = SPI Data Register is Empty 1 = SPI Master was selected as Slave HCS 12 Technical Training, Rev 2. 0 Module 7 - SCI, Slide 25 MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.

SPI Clocks SS SCK (CPHA=0) CPOL = 0 IDLE LO SCK (CPHA=1) SCK CPOL = 1 IDLE HI SCK (CPHA=0) (CPHA=1) MISO/ MOSI MSB 6 5 4 3 2 1 LSB INTERNAL STROBE FOR DATA CAPTURE CPHA = 1 Latch bits on second edge of each SCK cycle CPHA = 0 Latch bits on first edge of each SCK cycle • MASTER asserts SS in software BEFORE transfer is initiated HCS 12 Technical Training, Rev 2. 0 Module 7 - SCI, Slide 26 MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.

SPI Registers (3 of 3) SPICR 2 - SPI Control Register 2 Address offset $0001 MODFEN - Mode Fault Enable 0 = Mode Fault Disabled 1 = Mode Fault Enabled BIDIROE - Output Enable in Bidirectional mode 0 = Output Buffer Disabled 1 = Output Buffer Enabled SPISWAI = SPI Stop in Wait Mode 1 = HALT SSI CLOCK WHEN CPU IN WAIT MODE SERIAL PIN CONFIGURATION WITH MSTR CONTROL BIT PIN MODE SPC 0 MSTR MISO MOSI SCK SS NORMAL 0 0 1 1 0 1 BIDIRECTIONAL SLAVE OUT MSTR IN SLAVE IN SCKI SSI MSTR OUT SCKOUT SS I/O SCKI SSI SLAVEI/O ---- ---MSTRI/O SCKOUT SS I/O HCS 12 Technical Training, Rev 2. 0 Module 7 - SCI, Slide 27 MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.

SPI Modes MASTER NORMAL MODE Transmitter MOSI Transmitter SPI BIDIRECTIONAL MODE SPI DDRS 5 MISO Receiver DDRS 5 Receiver SPC 0 = 0 SPC 0 = 1 NORMAL MODE SLAVE Transmitter SPI MIMO MISO GPIO BIDIRECTIONAL MODE Transmitter SPI DDRS 5 Receiver MOSI PS 4 SISO DDRS 5 Receiver SPC 0 = 0 SPC 0 = 1 PS 5 GPIO STATION #1 STATION #2 STATION #3 SWOM - ENABLES OPEN DRAIN OUTPUT TX RX SINGLE-WIRE COMMUNICATIONS HCS 12 Technical Training, Rev 2. 0 Module 7 - SCI, Slide 28 MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.

SPI Flags Interrupts: for SPI data transfers and mode fault • To clear SPI data transfer flag (SPIF), read SPSR followed by an access of SPDR. • To clear mode fault flag (MODF), read SPSR followed by a write to SPCR • SPI vector is used Reset conditions: - SPI is disabled - Slave mode - Port s output buffers are normal - Interrupts are disabled - Flag bits are cleared HCS 12 Technical Training, Rev 2. 0 Module 7 - SCI, Slide 29 MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.

SPI Application Examples HCS 12 SPI +5 V 0. 1 u. F SS 0 MC 14489 7 -seg. driver SS 1 MC 14489 7 -seg. driver SS 2 MISO MOSI MC 145050 11 chan. A/D 7 -segment display x 5 V DD SS 11 ANALOG H C S 1 2 M C 1 CS 4 SCLK 5 0 MOSI 5 0 MISO SS SCLK MOSI MISO Photocell +5 V AN 10 AN 9 AN 8 AN 7 AN 6 AN 5 AN 4 AN 3 AN 2 AN 1 AN 0 INPUTS VOLTAGE PRESSURE TEMPRATURE 0. 2 u. F ATD CLK Gas Pedal SCK 2 MHZ OSC Switches Thermistors SS Peripheral Chip Select MISO Master-In, Slave-Out Data MOSI Master-Out, Slave-In Data SCK Shift Clock SERIAL DATA_1 DLY BETWEEN CONVERSION SERIAL DATA_2 IS MININUM OF 44 ADC CLKS HCS 12 Technical Training, Rev 2. 0 Module 7 - SCI, Slide 30 MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.