Sequential Logic Implementation z Sequential Circuits y Primitive

  • Slides: 73
Download presentation
Sequential Logic Implementation z Sequential Circuits y Primitive sequential elements y Combinational logic z

Sequential Logic Implementation z Sequential Circuits y Primitive sequential elements y Combinational logic z Models for representing sequential circuits y Finite-state machines (Moore and Mealy) y Representation of memory (states) y Changes in state (transitions) z Basic sequential circuits y Shift registers y Counters z Design procedure y State diagrams y State transition table y Next state functions CS 150 - Fall 2000 - Sequential Logic Implementation - 1

Abstraction of State Elements z Divide circuit into combinational logic and state z Localize

Abstraction of State Elements z Divide circuit into combinational logic and state z Localize feedback loops and make it easy to break cycles z Implementation of storage elements leads to various forms of sequential logic Inputs Combinational Logic State Inputs Outputs State Outputs Storage Elements CS 150 - Fall 2000 - Sequential Logic Implementation - 2

Forms of Sequential Logic z Asynchronous sequential logic – state changes occur whenever state

Forms of Sequential Logic z Asynchronous sequential logic – state changes occur whenever state inputs change (elements may be simple wires or delay elements) z Synchronous sequential logic – state changes occur in lock step across all storage elements (using a periodic waveform - the clock) Clock CS 150 - Fall 2000 - Sequential Logic Implementation - 3

Finite State Machine Representations z States: determined by possible values in sequential storage elements

Finite State Machine Representations z States: determined by possible values in sequential storage elements z Transitions: change of state z Clock: controls when state can change by controlling storage elements 010 001 In = 0 z Sequential Logic In = 1 100 111 In = 0 In = 1 110 y Sequences through a series of states y Based on sequence of values on input signals y Clock period defines elements of sequence CS 150 - Fall 2000 - Sequential Logic Implementation - 4

Example Finite State Machine Diagram z Combination lock from first lecture ERR closed not

Example Finite State Machine Diagram z Combination lock from first lecture ERR closed not equal & new reset S 1 closed mux=C 1 equal & new not new S 2 closed mux=C 2 equal & new not equal & new S 3 closed mux=C 3 equal & new not new CS 150 - Fall 2000 - Sequential Logic Implementation - 5 OPEN open

Can Any Sequential System be Represented with a State Diagram? z Shift Register y

Can Any Sequential System be Represented with a State Diagram? z Shift Register y Input value shown on transition arcs y Output values shown within state node OUT 1 0 0 0 001 D Q 110 101 0 0 1 1 1 010 1 000 D Q OUT 3 CLK 100 1 D Q IN OUT 2 111 0 011 CS 150 - Fall 2000 - Sequential Logic Implementation - 6 1

Counters are Simple Finite State Machines z Counters y Proceed thru well-defined state sequence

Counters are Simple Finite State Machines z Counters y Proceed thru well-defined state sequence in response to enable z Many types of counters: binary, BCD, Gray-code y 3 -bit up-counter: 000, 001, 010, 011, 100, 101, 110, 111, 000, . . . y 3 -bit down-counter: 111, 110, 101, 100, 011, 010, 001, 000, 111, . . . 001 000 011 100 3 -bit up-counter 111 110 101 CS 150 - Fall 2000 - Sequential Logic Implementation - 7

How Do We Turn a State Diagram into Logic? z Counter y Three flip-flops

How Do We Turn a State Diagram into Logic? z Counter y Three flip-flops to hold state y Logic to compute next state y Clock signal controls when flip-flop memory can change x. Wait long enough for combinational logic to compute new value x. Don't wait too long as that is low performance OUT 1 D Q OUT 2 D Q CLK "1" CS 150 - Fall 2000 - Sequential Logic Implementation - 8 OUT 3 D Q

FSM Design Procedure z Start with counters y Simple because output is just state

FSM Design Procedure z Start with counters y Simple because output is just state y Simple because no choice of next state based on input z State diagram to state transition table y Tabular form of state diagram y Like a truth-table z State encoding y Decide on representation of states y For counters it is simple: just its value z Implementation y Flip-flop for each state bit y Combinational logic based on encoding CS 150 - Fall 2000 - Sequential Logic Implementation - 9

FSM Design Procedure: State Diagram to Encoded State Transition Table z Tabular form of

FSM Design Procedure: State Diagram to Encoded State Transition Table z Tabular form of state diagram z Like a truth-table (specify output for all input combinations) z Encoding of states: easy for counters – just use value 001 000 011 100 3 -bit up-counter 111 110 101 current state 0 000 1 001 2 010 3 011 4 100 5 101 6 110 7 111 CS 150 - Fall 2000 - Sequential Logic Implementation - 10 next state 001 1 010 2 011 3 100 4 101 5 110 6 111 7 000 0

Implementation z D flip-flop for each state bit z Combinational logic based on encoding

Implementation z D flip-flop for each state bit z Combinational logic based on encoding C 3 0 0 1 1 C 2 0 0 1 1 C 1 0 1 0 1 N 3 C 1 N 3 0 0 0 1 1 0 C 3 0 0 1 1 0 1 C 2 N 2 0 1 1 0 N 1 1 0 1 0 N 1 : = C 1' N 2 : = C 1 C 2' + C 1'C 2 : = C 1 xor C 2 N 3 : = C 1 C 2 C 3' + C 1'C 3 + C 2'C 3 : = C 1 C 2 C 3' + (C 1' + C 2')C 3 : = (C 1 C 2) xor C 3 N 2 C 1 notation to show function represent input to D-FF C 3 0 1 1 0 0 1 N 1 C 2 CS 150 - Fall 2000 - Sequential Logic Implementation - 11 C 3 1 1 0 0 C 2

Implementation (cont'd) z Programmable Logic Building Block for Sequential Logic y Macro-cell: FF +

Implementation (cont'd) z Programmable Logic Building Block for Sequential Logic y Macro-cell: FF + logic x. D-FF x. Two-level logic capability like PAL (e. g. , 8 product terms) DQ Q CS 150 - Fall 2000 - Sequential Logic Implementation - 12

Another Example z Shift Register y Input determines next state In 0 0 0

Another Example z Shift Register y Input determines next state In 0 0 0 0 1 1 1 1 C 1 0 0 0 0 1 1 1 1 C 2 0 0 1 1 C 3 0 1 0 1 N 1 0 0 0 0 1 1 1 1 N 2 0 0 0 0 1 1 1 1 N 3 0 0 1 1 1 100 0 101 0 0 001 N 1 : = In N 2 : = C 1 N 3 : = C 2 IN 0 OUT 1 D Q 1 1 1 010 1 000 110 D Q CLK CS 150 - Fall 2000 - Sequential Logic Implementation - 13 111 0 011 OUT 2 D Q OUT 3 1

More Complex Counter Example z Complex Counter y Repeats five states in sequence y

More Complex Counter Example z Complex Counter y Repeats five states in sequence y Not a binary number representation z Step 1: Derive the state transition diagram y Count sequence: 000, 011, 101, 110 z Step 2: Derive the state transition table from the state transition diagram 000 110 010 101 011 Present State Next State C B A C+ B+ A+ 0 0 1 0 0 0 1 – – – 0 1 0 0 1 1 1 0 0 – – – 1 0 1 1 0 0 1 1 1 – – – note the don't care conditions that arise from the unused state codes CS 150 - Fall 2000 - Sequential Logic Implementation - 14

More Complex Counter Example (cont’d) z Step 3: K-maps for Next State Functions C+

More Complex Counter Example (cont’d) z Step 3: K-maps for Next State Functions C+ A B+ C 0 0 0 X X 1 A A+ C 1 1 0 X X 0 X 1 B B C+ : = A B+ : = B' + A'C' A+ : = BC' CS 150 - Fall 2000 - Sequential Logic Implementation - 15 A C 0 1 0 X X 1 X 0 B

Self-Starting Counters (cont’d) z Re-deriving state transition table from don't care assignment C+ A

Self-Starting Counters (cont’d) z Re-deriving state transition table from don't care assignment C+ A B+ C 0 0 1 1 A A+ C 1 1 0 0 1 A C 0 1 0 0 B B Present State Next State C B A C+ B+ A+ 0 0 1 0 0 0 1 1 1 0 0 1 1 0 0 0 1 0 1 1 1 0 0 0 0 1 1 0 0 B 111 000 110 100 010 101 011 CS 150 - Fall 2000 - Sequential Logic Implementation - 16

Self-Starting Counters z Start-up States y At power-up, counter may be in an unused

Self-Starting Counters z Start-up States y At power-up, counter may be in an unused or invalid state y Designer must guarantee it (eventually) enters a valid state z Self-starting Solution y Design counter so that invalid states eventually transition to a valid state y May limit exploitation of don't cares 111 001 000 implementation on previous slide 000 110 001 110 100 010 101 010 011 CS 150 - Fall 2000 - Sequential Logic Implementation - 17 101 011

State Machine Model z Values stored in registers represent the state of the circuit

State Machine Model z Values stored in registers represent the state of the circuit z Combinational logic computes: y Next state x. Function of current state and inputs y Outputs x. Function of current state and inputs (Mealy machine) x. Function of current state only (Moore machine) Inputs output logic next state logic Outputs Next State Current State CS 150 - Fall 2000 - Sequential Logic Implementation - 18

State Machine Model (cont’d) output logic Inputs Outputs next state logic Next State z

State Machine Model (cont’d) output logic Inputs Outputs next state logic Next State z States: S 1, S 2, . . . , Sk z Inputs: I 1, I 2, . . . , Im Current State z Outputs: O 1, O 2, . . . , On z Transition function: Fs(Si, Ij) z Output function: Fo(Si) or Fo(Si, Ij) Next State Clock 0 1 2 3 4 CS 150 - Fall 2000 - Sequential Logic Implementation - 19 5

Example: Ant Brain (Ward, MIT) z Sensors: z Actuators: z Goal: z Strategy: L

Example: Ant Brain (Ward, MIT) z Sensors: z Actuators: z Goal: z Strategy: L and R antennae, 1 if in touching wall F - forward step, TL/TR - turn left/right slightly find way out of maze keep the wall on the right CS 150 - Fall 2000 - Sequential Logic Implementation - 20

Ant Behavior A: Following wall, touching Go forward, turning left slightly C: Break in

Ant Behavior A: Following wall, touching Go forward, turning left slightly C: Break in wall Go forward, turning right slightly E: Wall in front Turn left until. . . LOST: Forward until we touch something B: Following wall, not touching Go forward, turning right slightly D: Hit wall again Back to state A F: . . . we are here, same as state B G: Turn left until. . . CS 150 - Fall 2000 - Sequential Logic Implementation - 21

Designing an Ant Brain z State Diagram L+R LOST (F) L’ R’ L+R L’

Designing an Ant Brain z State Diagram L+R LOST (F) L’ R’ L+R L’ R L E/G (TL) L’ R’ A (TL, F) R R L’ R’ B (TR, F) R’ C (TR, F) CS 150 - Fall 2000 - Sequential Logic Implementation - 22 R’

Synthesizing the Ant Brain Circuit z Encode States Using a Set of State Variables

Synthesizing the Ant Brain Circuit z Encode States Using a Set of State Variables y Arbitrary choice - may affect cost, speed z Use Transition Truth Table y Define next state function for each state variable y Define output function for each output z Implement next state and output functions using combinational logic y 2 -level logic (ROM/PLA/PAL) y Multi-level logic y Next state and output functions can be optimized together CS 150 - Fall 2000 - Sequential Logic Implementation - 23

Transition Truth Table z Using symbolic states and outputs LOST (F) L’ R’ L+R

Transition Truth Table z Using symbolic states and outputs LOST (F) L’ R’ L+R L’ R E/G (TL) L’ R’ A (TL, F) L R L’ R’ state LOST A A A B B. . . L 0 – 1 0 0 1 – –. . . R 0 1 – 0 1. . . next state LOST E/G B A E/G C A. . . outputs F F F TL, F TR, F. . . B (TR, F) R’ CS 150 - Fall 2000 - Sequential Logic Implementation - 24 R C (TR, F) R’

Synthesis z 5 states : at least 3 state variables required (X, Y, Z)

Synthesis z 5 states : at least 3 state variables required (X, Y, Z) y State assignment (in this case, arbitrarily chosen) state X, Y, Z 000. . . 010 010 011. . . L R 0 0 0 1. . . 0 0 0 1 1 0 0 0 1. . . next state X', Y', Z' 000 001. . . 011 010 001 100 010. . . outputs F TR TL 1 0 0. . . 1 0 1 1 1 0. . . it now remains to synthesize these 6 functions CS 150 - Fall 2000 - Sequential Logic Implementation - 25 LOST E/G A B C - 000 001 010 011 100

Synthesis of Next State and Output Functions state X, Y, Z 000 000 001

Synthesis of Next State and Output Functions state X, Y, Z 000 000 001 001 010 010 011 100 inputs L R 0 0 - 1 1 0 0 0 1 1 - 0 - 1 next state X+, Y+, Z+ 000 001 011 010 001 100 010 outputs F TR TL 1 0 0 1 0 0 1 1 0 1 1 0 e. g. TR = X + Y Z X+ = X R’ + Y Z R’ = R’ TR CS 150 - Fall 2000 - Sequential Logic Implementation - 26

Circuit Implementation z Outputs are a function of the current state only Moore machine

Circuit Implementation z Outputs are a function of the current state only Moore machine F TR TL output logic L R next state logic Current State Next State X+ Y+ Z+ X Y Z CS 150 - Fall 2000 - Sequential Logic Implementation - 27

Don’t Cares in FSM Synthesis z What happens to the "unused" states (101, 110,

Don’t Cares in FSM Synthesis z What happens to the "unused" states (101, 110, 111)? z Exploited as don't cares to minimize the logic y If states can't happen, then don't care what the functions do y if states do happen, we may be in trouble L’ R’ 000 (F) L+R 101 001 (TL) L’ R’ L’ R 010 (TL, F) L R R L’ R’ 011 (TR, F) 110 111 Ant is in deep trouble if it gets in this state R’ 100 (TR, F) CS 150 - Fall 2000 - Sequential Logic Implementation - 28 R’

State Minimization z Fewer states may mean fewer state variables z High-level synthesis may

State Minimization z Fewer states may mean fewer state variables z High-level synthesis may generate many redundant states z Two state are equivalent if they are impossible to distinguish from the outputs of the FSM, i. e. , for any input sequence the outputs are the same z Two conditions for two states to be equivalent: y 1) Output must be the same in both states y 2) Must transition to equivalent states for all input combinations CS 150 - Fall 2000 - Sequential Logic Implementation - 29

Ant Brain Revisited z Any equivalent states? L+R LOST (F) L’ R’ L+R L’

Ant Brain Revisited z Any equivalent states? L+R LOST (F) L’ R’ L+R L’ R L E/G (TL) L’ R’ A (TL, F) R R L’ R’ B (TR, F) R’ C (TR, F) CS 150 - Fall 2000 - Sequential Logic Implementation - 30 R’

New Improved Brain z Merge equivalent B and C states z Behavior is exactly

New Improved Brain z Merge equivalent B and C states z Behavior is exactly the same as the 5 -state brain z We now need only 2 state variables rather than 3 L+R LOST (F) L+R L’ R’ L’ R L E/G (TL) L’ R’ A (TL, F) R L’ R’ R’ B/C (TR, F) CS 150 - Fall 2000 - Sequential Logic Implementation - 31

New Brain Implementation state X, Y 00 00 00 01 01 01 10 10

New Brain Implementation state X, Y 00 00 00 01 01 01 10 10 10 11 11 inputs L R 0 0 - 1 1 0 0 0 1 1 - 0 - 1 next state outputs X', Y' F TR TL 00 1 0 0 01 1 0 0 1 01 0 0 1 11 1 0 1 10 1 01 1 0 1 11 1 1 0 10 1 1 0 X+ L X 0 0 1 0 0 0 1 1 Y+ 1 1 0 0 R L X 0 1 1 0 0 0 Y F L X 1 1 0 0 1 1 Y 1 1 1 0 0 1 1 R Y TR R L X 0 0 0 0 1 1 Y CS 150 - Fall 2000 - Sequential Logic Implementation - 32 0 0 TL R L X 0 0 1 1 0 0 Y 1 1 R

Mealy vs. Moore Machines z Moore: outputs depend on current state only z Mealy:

Mealy vs. Moore Machines z Moore: outputs depend on current state only z Mealy: outputs depend on current state and inputs z Ant brain is a Moore Machine y Output does not react immediately to input change z We could have specified a Mealy FSM y Outputs have immediate reaction to inputs y As inputs change, so does next state, doesn’t commit until clocking event L’ R / TL, F L / TL A react right away to leaving the wall L’ R’ / TR, F CS 150 - Fall 2000 - Sequential Logic Implementation - 33

Specifying Outputs for a Moore Machine z Output is only function of state y

Specifying Outputs for a Moore Machine z Output is only function of state y Specify in state bubble in state diagram y Example: sequence detector for 01 or 10 0 1 B/0 D/1 0 reset 0 1 A/0 0 1 1 C/0 1 0 E/1 reset 1 0 0 0 0 0 input – 0 1 0 1 0 1 current state – A A B B C C D D E E CS 150 - Fall 2000 - Sequential Logic Implementation - 34 next state A B C B D E C B D output 0 0 0 1 1

Specifying Outputs for a Mealy Machine z Output is function of state and inputs

Specifying Outputs for a Mealy Machine z Output is function of state and inputs y Specify output on transition arc between states y Example: sequence detector for 01 or 10 0/0 B 0/0 reset/0 0/1 A 1/1 1/0 reset 1 0 0 0 input – 0 1 0 1 current state – A A B B C C C 1/0 CS 150 - Fall 2000 - Sequential Logic Implementation - 35 next state A B C B C output 0 0 1 1 0

Comparison of Mealy and Moore Machines z Mealy Machines tend to have less states

Comparison of Mealy and Moore Machines z Mealy Machines tend to have less states y Different outputs on arcs (n^2) rather than states (n) z Moore Machines are safer to use y Outputs change at clock edge (always one cycle later) y In Mealy machines, input change can cause output change as soon as logic is done – a big problem when two machines are interconnected – asynchronous feedback z Mealy Machines react faster to inputs y React in same cycle – don't need to wait for clock y In Moore machines, more logic may be necessary to decode state into outputs – more gate delays after inputs combinational logic for next state feedback logic for outputs inputs reg logic for outputs combinational logic for next state feedback CS 150 - Fall 2000 - Sequential Logic Implementation - 36 outputs reg

Mealy and Moore Examples z Recognize A, B = 0, 1 y Mealy or

Mealy and Moore Examples z Recognize A, B = 0, 1 y Mealy or Moore? CS 150 - Fall 2000 - Sequential Logic Implementation - 37

Mealy and Moore Examples (cont’d) z Recognize A, B = 1, 0 then 0,

Mealy and Moore Examples (cont’d) z Recognize A, B = 1, 0 then 0, 1 y Mealy or Moore? CS 150 - Fall 2000 - Sequential Logic Implementation - 38

Registered Mealy Machine (Really Moore) z Synchronous (or registered) Mealy Machine y Registered state

Registered Mealy Machine (Really Moore) z Synchronous (or registered) Mealy Machine y Registered state AND outputs y Avoids ‘glitchy’ outputs y Easy to implement in PLDs z Moore Machine with no output decoding y Outputs computed on transition to next state rather than after entering y View outputs as expanded state vector Inputs output logic next state logic Current State CS 150 - Fall 2000 - Sequential Logic Implementation - 39 Outputs

Example: Vending Machine z Release item after 15 cents are deposited z Single coin

Example: Vending Machine z Release item after 15 cents are deposited z Single coin slot for dimes, nickels z No change Reset N Coin Sensor D Vending Machine FSM Open Release Mechanism Clock CS 150 - Fall 2000 - Sequential Logic Implementation - 40

Example: Vending Machine (cont’d) z Suitable Abstract Representation Reset y Tabulate typical input sequences:

Example: Vending Machine (cont’d) z Suitable Abstract Representation Reset y Tabulate typical input sequences: x 3 nickels xnickel, dime xdime, nickel xtwo dimes S 0 N S 1 y Draw state diagram: x. Inputs: N, D, reset x. Output: open chute y Assumptions: x. Assume N and D asserted for one cycle x. Each state has a self loop for N = D = 0 (no coin) D N S 3 S 2 D N S 4 [open] S 5 [open] N S 7 [open] CS 150 - Fall 2000 - Sequential Logic Implementation - 41 D S 6 [open]

Example: Vending Machine (cont’d) z Minimize number of states - reuse states whenever possible

Example: Vending Machine (cont’d) z Minimize number of states - reuse states whenever possible present state 0¢ Reset 0¢ 5¢ N D 5¢ 10¢ N D 10¢ N+D 15¢ [open] 15¢ inputs D N 0 0 0 1 1 0 0 0 1 1 – – next state 0¢ 5¢ 10¢ – 5¢ 10¢ 15¢ – 15¢ symbolic state table CS 150 - Fall 2000 - Sequential Logic Implementation - 42 output open 0 0 0 – 1

Example: Vending Machine (cont’d) z Uniquely Encode States present state inputs Q 1 Q

Example: Vending Machine (cont’d) z Uniquely Encode States present state inputs Q 1 Q 0 D N 0 0 0 1 1 0 1 0 0 0 1 1 1 0 0 1 1 – – next D 1 0 0 1 – 0 1 1 – 1 state D 0 0 1 0 – 1 0 1 – 0 1 1 – 1 output open 0 0 0 – 1 CS 150 - Fall 2000 - Sequential Logic Implementation - 43

Example: Vending Machine (cont’d) z Mapping to Logic Q 1 D 1 0 0

Example: Vending Machine (cont’d) z Mapping to Logic Q 1 D 1 0 0 1 1 1 D X X 1 1 Q 0 Q 1 D 0 Q 1 Open 0 0 1 1 N D X X 0 0 1 0 N 0 1 1 1 D X X N 0 0 1 0 Q 0 D 1 = Q 1 + D + Q 0 N D 0 = Q 0’ N + Q 0 N’ + Q 1 N + Q 1 D OPEN = Q 1 Q 0 CS 150 - Fall 2000 - Sequential Logic Implementation - 44

Example: Vending Machine (cont’d) z One-hot Encoding present state Q 3 Q 2 Q

Example: Vending Machine (cont’d) z One-hot Encoding present state Q 3 Q 2 Q 1 Q 0 0 1 0 0 0 1 1 0 0 0 inputs D N 0 0 0 1 1 0 0 0 1 1 - - next state D 3 D 2 D 1 0 0 0 1 0 - - 0 0 1 0 1 0 0 - - 0 1 0 0 - - 1 0 0 output D 0 open 1 0 0 0 0 0 1 D 0 = Q 0 D’ N’ D 1 = Q 0 N + Q 1 D’ N’ D 2 = Q 0 D + Q 1 N + Q 2 D’ N’ D 3 = Q 1 D + Q 2 N + Q 3 OPEN = Q 3 CS 150 - Fall 2000 - Sequential Logic Implementation - 45

Equivalent Mealy and Moore State Diagrams z Moore machine y outputs associated with state

Equivalent Mealy and Moore State Diagrams z Moore machine y outputs associated with state N’ D’ + Reset 0¢ [0] Mealy machine outputs associated with transitions 0¢ N’ D’ N D N’ D’/0 N/0 5¢ [0] N’ D’ D/0 N D (N’ D’ + Reset)/0 Reset/0 5¢ N’ D’/0 10¢ N’ D’/0 15¢ Reset’/1 N/0 10¢ [0] N’ D’ N+D D/1 N+D/1 15¢ [1] Reset’ CS 150 - Fall 2000 - Sequential Logic Implementation - 46

Example: Traffic Light Controller z A busy highway is intersected by a little used

Example: Traffic Light Controller z A busy highway is intersected by a little used farmroad z Detectors C sense the presence of cars waiting on the farmroad y with no car on farmroad, light remain green in highway direction y if vehicle on farmroad, highway lights go from Green to Yellow to Red, allowing the farmroad lights to become green y these stay green only as long as a farmroad car is detected but never longer than a set interval y when these are met, farm lights transition from Green to Yellow to Red, allowing highway to return to green y even if farmroad vehicles are waiting, highway gets at least a set interval as green z Assume you have an interval timer that generates: y a short time pulse (TS) and y a long time pulse (TL), y in response to a set (ST) signal. y TS is to be used for timing yellow lights and TL for green lights CS 150 - Fall 2000 - Sequential Logic Implementation - 47

Example: Traffic Light Controller (cont’) z Highway/farm road intersection farm road car sensors highway

Example: Traffic Light Controller (cont’) z Highway/farm road intersection farm road car sensors highway CS 150 - Fall 2000 - Sequential Logic Implementation - 48

Example: Traffic Light Controller (cont’) z Tabulation of Inputs and Outputs inputs reset C

Example: Traffic Light Controller (cont’) z Tabulation of Inputs and Outputs inputs reset C TS TL description place FSM in initial state detect vehicle on the farm road short time interval expired long time interval expired outputs description HG, HY, HR assert green/yellow/red highway lights FG, FY, FR assert green/yellow/red highway lights ST start timing a short or long interval z Tabulation of unique states – some light configurations imply others state S 0 S 1 S 2 S 3 description highway green (farm road red) highway yellow (farm road red) farm road green (highway red) farm road yellow (highway red) CS 150 - Fall 2000 - Sequential Logic Implementation - 49

Example: Traffic Light Controller (cont’) z State Diagram Reset (TL • C)' S 0

Example: Traffic Light Controller (cont’) z State Diagram Reset (TL • C)' S 0 TL • C / ST TS / ST S 0: HG S 1: HY TS' S 1 S 3 S 2: FG S 3: FY TS / ST TL+C' / ST S 2 (TL+C')' CS 150 - Fall 2000 - Sequential Logic Implementation - 50 TS'

Example: Traffic Light Controller (cont’) z Generate state table with symbolic states z Consider

Example: Traffic Light Controller (cont’) z Generate state table with symbolic states z Consider state assignments Inputs C TL 0 – – 0 1 1 – – 1 0 0 – – 1 – – SA 1: SA 2: SA 3: Present State TS – – – 0 1 HG HG HG HY HY FG FG FG FY FY HG = 0001 Next State HG HG HY HY FG FG FY FY FY HG HY = 01 HY = 10 HY = 0010 FG = 11 FG = 0100 output encoding – similar problem to state assignment (Green = 00, Yellow = 01, Red = 10) Outputs ST H 0 Green 1 Green 0 Yellow 1 Yellow 0 Red 1 Red FY = 10 FY = 11 FY = 1000 CS 150 - Fall 2000 - Sequential Logic Implementation - 51 F Red Red Red Green Yellow (one-hot)

Logic for Different State Assignments z SA 1 NS 1 = C • TL'

Logic for Different State Assignments z SA 1 NS 1 = C • TL' • PS 1 • PS 0 + TS • PS 1' • PS 0 + TS • PS 1 • PS 0' + C' • PS 1 • PS 0 + TL • PS 1 • PS 0 NS 0 = C • TL • PS 1' • PS 0' + C • TL' • PS 1 • PS 0 + PS 1' • PS 0 ST = C • TL • PS 1' • PS 0' + TS • PS 1' • PS 0 + TS • PS 1 • PS 0' + C' • PS 1 • PS 0 + TL • PS 1 • PS 0 H 1 = PS 1 H 0 = PS 1' • PS 0 F 1 = PS 1' F 0 = PS 1 • PS 0' z SA 2 NS 1 = C • TL • PS 1' + TS' • PS 1 + C' • PS 1' • PS 0 NS 0 = TS • PS 1 • PS 0' + PS 1' • PS 0 + TS' • PS 1 • PS 0 ST = C • TL • PS 1' + C' • PS 1' • PS 0 + TS • PS 1 H 1 = PS 0 H 0 = PS 1 • PS 0' F 1 = PS 0' F 0 = PS 1 • PS 0 z SA 3 NS 3 = C' • PS 2 + TL • PS 2 + TS' • PS 3 NS 1 = C • TL • PS 0 + TS' • PS 1 NS 2 = TS • PS 1 + C • TL' • PS 2 NS 0 = C' • PS 0 + TL' • PS 0 + TS • PS 3 ST = C • TL • PS 0 + TS • PS 1 + C' • PS 2 + TL • PS 2 + TS • PS 3 H 1 = PS 3 + PS 2 H 0 = PS 1 F 1 = PS 1 + PS 0 F 0 = PS 3 CS 150 - Fall 2000 - Sequential Logic Implementation - 52

Vending Machine Example (PLD mapping) D 0 D 1 OPEN = reset'(Q 0'N +

Vending Machine Example (PLD mapping) D 0 D 1 OPEN = reset'(Q 0'N + Q 0 N' + Q 1 N + Q 1 D) = reset'(Q 1 + D + Q 0 N) = Q 1 Q 0 CLK Q 0 DQ Seq N Q 1 DQ Seq D Open DQ Com Reset CS 150 - Fall 2000 - Sequential Logic Implementation - 53

Vending Machine (cont’d) z OPEN = Q 1 Q 0 creates a combinational delay

Vending Machine (cont’d) z OPEN = Q 1 Q 0 creates a combinational delay after Q 1 and Q 0 change z This can be corrected by retiming, i. e. , move flip-flops and logic through each other to improve delay z OPEN = reset'(Q 1 + D + Q 0 N)(Q 0'N + Q 0 N' + Q 1 N + Q 1 D) = reset'(Q 1 Q 0 N' + Q 1 N + Q 1 D + Q 0'ND + Q 0 N'D) z Implementation now looks like a synchronous Mealy machine y Common for programmable devices to have FF at end of logic CS 150 - Fall 2000 - Sequential Logic Implementation - 54

Vending Machine (Retimed PLD Mapping) OPEN = reset'(Q 1 Q 0 N' + Q

Vending Machine (Retimed PLD Mapping) OPEN = reset'(Q 1 Q 0 N' + Q 1 N + Q 1 D + Q 0'ND + Q 0 N'D) CLK Q 0 DQ Seq N Q 1 DQ Seq D OPEN Open DQ Seq Reset CS 150 - Fall 2000 - Sequential Logic Implementation - 55

Finite State Machine Optimization z State Minimization y Fewer states require fewer state bits

Finite State Machine Optimization z State Minimization y Fewer states require fewer state bits y Fewer bits require fewer logic equations z Encodings: State, Inputs, Outputs y State encoding with fewer bits has fewer equations to implement x. However, each may be more complex y State encoding with more bits (e. g. , one-hot) has simpler equations x. Complexity directly related to complexity of state diagram y Input/output encoding may or may not be under designer control CS 150 - Fall 2000 - Sequential Logic Implementation - 56

Algorithmic Approach to State Minimization z Goal – identify and combine states that have

Algorithmic Approach to State Minimization z Goal – identify and combine states that have equivalent behavior z Equivalent States: y Same output y For all input combinations, states transition to same or equivalent states z Algorithm Sketch y 1. Place all states in one set y 2. Initially partition set based on output behavior y 3. Successively partition resulting subsets based on next state transitions y 4. Repeat (3) until no further partitioning is required xstates left in the same set are equivalent y Polynomial time procedure CS 150 - Fall 2000 - Sequential Logic Implementation - 57

State Minimization Example z Sequence Detector for 010 or 110 0/0 S 3 0/0

State Minimization Example z Sequence Detector for 010 or 110 0/0 S 3 0/0 S 1 1/0 S 0 0/0 S 4 S 5 0/1 Next State Present State X=0 X=1 Output X=0 X=1 Reset 0 1 00 01 10 11 S 0 S 1 S 2 S 3 S 4 S 5 S 6 0 0 1 0 1 S 3 S 5 S 0 S 0 S 2 S 4 S 6 S 0 S 0 1/0 1/0 Input Sequence 0/0 S 2 1/0 S 6 0/1 1/0 CS 150 - Fall 2000 - Sequential Logic Implementation - 58 0 0 0 0

Method of Successive Partitions Input Sequence Next State Present State X=0 X=1 Output X=0

Method of Successive Partitions Input Sequence Next State Present State X=0 X=1 Output X=0 X=1 Reset 0 1 00 01 10 11 S 0 S 1 S 2 S 3 S 4 S 5 S 6 0 0 1 0 1 S 3 S 5 S 0 S 0 ( S 0 S 1 S 2 S 3 S 4 S 5 S 6 ) ( S 0 S 1 S 2 S 3 S 5 ) ( S 4 S 6 ) ( S 0 S 3 S 5 ) ( S 1 S 2 ) ( S 4 S 6 ) S 2 S 4 S 6 S 0 S 0 0 0 0 0 S 1 is equivalent to S 2 S 3 is equivalent to S 5 S 4 is equivalent to S 6 ( S 0 ) ( S 3 S 5 ) ( S 1 S 2 ) ( S 4 S 6 ) CS 150 - Fall 2000 - Sequential Logic Implementation - 59

Minimized FSM z State minimized sequence detector for 010 or 110 Input Sequence Next

Minimized FSM z State minimized sequence detector for 010 or 110 Input Sequence Next State Present State X=0 X=1 Output X=0 X=1 Reset 0+1 X 0 X 1 S 0 S 1' S 3' S 4' 0 0 0 1 S 1' S 3' S 0 S 1' S 4' S 0 S 0 X/0 0/0 S 1’ 1/0 S 4’ S 3’ X/0 0/1 1/0 CS 150 - Fall 2000 - Sequential Logic Implementation - 60 0 0

More Complex State Minimization z Multiple input example inputs here 00 10 00 S

More Complex State Minimization z Multiple input example inputs here 00 10 00 S 0 [1] 01 10 S 2 [1] 01 11 10 01 S 4 [1] S 3 [0] 11 10 10 00 present state S 0 S 1 S 2 S 3 S 4 S 5 11 00 01 01 11 00 10 S 1 [0] 11 01 S 5 [0] 00 11 00 S 0 S 1 next state 01 10 11 S 2 S 3 S 1 S 4 S 3 S 2 S 4 S 0 S 4 S 5 S 1 S 2 S 5 S 4 S 0 S 5 symbolic state transition table CS 150 - Fall 2000 - Sequential Logic Implementation - 61 output 1 0 1 0

Minimized FSM z Implication Chart Method y Cross out incompatible states based on outputs

Minimized FSM z Implication Chart Method y Cross out incompatible states based on outputs y Then cross out more cells if indexed chart entries are already crossed out present state S 0' S 1 S 2 S 3' S 1 S 2 S 0 -S 1 S 1 -S 3 S 2 -S 2 S 3 -S 4 S 3 S 4 S 0 -S 0 S 1 -S 1 S 2 -S 2 S 3 -S 5 S 0 S 0 -S 1 S 3 -S 0 S 1 -S 4 S 4 -S 5 S 0 -S 1 S 3 -S 4 S 1 -S 0 S 4 -S 5 S 1 -S 0 S 3 -S 1 S 2 -S 2 S 4 -S 5 S 2 next state 00 01 10 11 S 0' S 1 S 2 S 3' S 0' S 3' S 1 S 3' S 2 S 0' S 1 S 0' S 3' minimized state table (S 0==S 4) (S 3==S 5) S 1 -S 1 S 0 -S 4 S 4 -S 0 S 5 -S 5 S 3 S 4 CS 150 - Fall 2000 - Sequential Logic Implementation - 62 output 1 0

Minimizing Incompletely Specified FSMs z Equivalence of states is transitive when machine is fully

Minimizing Incompletely Specified FSMs z Equivalence of states is transitive when machine is fully specified z But its not transitive when don't cares are present e. g. , state output S 0 S 1 S 2 – 0 1– – 1 S 1 is compatible with both S 0 and S 2 but S 0 and S 2 are incompatible z No polynomial time algorithm exists for determining best grouping of states into equivalent sets that will yield the smallest number of final states CS 150 - Fall 2000 - Sequential Logic Implementation - 63

Minimizing States May Not Yield Best Circuit z Example: edge detector - outputs 1

Minimizing States May Not Yield Best Circuit z Example: edge detector - outputs 1 when last two input changes from 0 to 1 X’ 00 [0] X’ 01 [1] X X’ 11 [0] X X 0 0 0 1 1 1 – Q 1 0 0 1 1 Q 0 0 1 1 0 Q 1+ 0 0 1 1 0 X Q 1+ = X (Q 1 xor Q 0) Q 0+ = X Q 1’ Q 0’ CS 150 - Fall 2000 - Sequential Logic Implementation - 64 Q 0+ 0 0 0 1 1 1 0

Another Implementation of Edge Detector z "Ad hoc" solution - not minimal but cheap

Another Implementation of Edge Detector z "Ad hoc" solution - not minimal but cheap and fast X’ X’ 10 [0] X’ 00 [0] X X 01 [1] X’ 11 [0] X X CS 150 - Fall 2000 - Sequential Logic Implementation - 65

State Assignment z Choose bit vectors to assign to each “symbolic” state y With

State Assignment z Choose bit vectors to assign to each “symbolic” state y With n state bits for m states there are 2 n! / (2 n – m)! [log n <= m <= 2 n] y 2 n codes possible for 1 st state, 2 n– 1 for 2 nd, 2 n– 2 for 3 rd, … y Huge number even for small values of n and m x. Intractable for state machines of any size x. Heuristics are necessary for practical solutions y Optimize some metric for the combinational logic x. Size (amount of logic and number of FFs) x. Speed (depth of logic and fanout) x. Dependencies (decomposition) CS 150 - Fall 2000 - Sequential Logic Implementation - 66

State Assignment Strategies z Possible Strategies y Sequential – just number states as they

State Assignment Strategies z Possible Strategies y Sequential – just number states as they appear in the state table y Random – pick random codes y One-hot – use as many state bits as there are states (bit=1 –> state) y Output – use outputs to help encode states y Heuristic – rules of thumb that seem to work in most cases z No guarantee of optimality – another intractable problem CS 150 - Fall 2000 - Sequential Logic Implementation - 67

One-hot State Assignment z Simple y Easy to encode, debug z Small Logic Functions

One-hot State Assignment z Simple y Easy to encode, debug z Small Logic Functions y Each state function requires only predecessor state bits as input z Good for Programmable Devices y Lots of flip-flops readily available y Simple functions with small support (signals its dependent upon) z Impractical for Large Machines y Too many states require too many flip-flops y Decompose FSMs into smaller pieces that can be one-hot encoded z Many Slight Variations to One-hot y One-hot + all-0 CS 150 - Fall 2000 - Sequential Logic Implementation - 68

Heuristics for State Assignment z Adjacent codes to states that share a common next

Heuristics for State Assignment z Adjacent codes to states that share a common next state y Group 1's in next state map a I i i Q a b Q+ c c O j k i/j c=i*a + i*b b i/k c z Adjacent codes to states that share a common ancestor state y Group 1's in next state map a I i k Q a a Q+ b c O j l i/j b=i *a c=k*a b k/l c z Adjacent codes to states that have a common output behavior y Group 1's in output map + I i i Q a c Q b d O j j j=i *a+ i *c b=i*a d=i*c CS 150 - Fall 2000 - Sequential Logic Implementation - 69 a c i/j b d

General Approach to Heuristic State Assignment z All current methods are variants of this

General Approach to Heuristic State Assignment z All current methods are variants of this y 1) Determine which states “attract” each other (weighted pairs) y 2) Generate constraints on codes (which should be in same cube) y 3) Place codes on Boolean cube so as to maximize constraints satisfied (weighted sum) z Different weights make sense depending on whether we are optimizing for two-level or multi-level forms z Can't consider all possible embeddings of state clusters in Boolean cube y Heuristics for ordering embedding y To prune search for best embedding y Expand cube (more state bits) to satisfy more constraints CS 150 - Fall 2000 - Sequential Logic Implementation - 70

Output-Based Encoding z Reuse outputs as state bits - use outputs to help distinguish

Output-Based Encoding z Reuse outputs as state bits - use outputs to help distinguish states y Why create new functions for state bits when output can serve as well y Fits in nicely with synchronous Mealy implementations Inputs C TL 0 – – 0 1 1 – – 1 0 0 – – 1 – – Present State TS – – – 0 1 HG HG HG HY HY FG FG FG FY FY HG = ST’ H 1’ H 0’ F 1 F 0’ + ST H 1 H 0’ F 1’ F 0 HY = ST H 1’ H 0’ F 1 F 0’ + ST’ H 1’ H 0 F 1 F 0’ FG = ST H 1’ H 0 F 1 F 0’ + ST’ H 1 H 0’ F 1’ F 0’ HY = ST H 1 H 0’ F 1’ F 0’ + ST’ H 1 H 0’ F 1’ F 0 Next State HG HG HY HY FG FG FY FY FY HG Outputs ST H 0 00 1 00 0 01 1 01 0 10 1 10 F 10 10 10 00 01 01 Output patterns are unique to states, we do not need ANY state bits – implement 5 functions (one for each output) instead of 7 (outputs plus 2 state bits) CS 150 - Fall 2000 - Sequential Logic Implementation - 71

Current State Assignment Approaches z For tight encodings using close to the minimum number

Current State Assignment Approaches z For tight encodings using close to the minimum number of state bits y Best of 10 random seems to be adequate (averages as well as heuristics) y Heuristic approaches are not even close to optimality y Used in custom chip design z One-hot encoding y Easy for small state machines y Generates small equations with easy to estimate complexity y Common in FPGAs and other programmable logic z Output-based encoding y Ad hoc - no tools y Most common approach taken by human designers y Yields very small circuits for most FSMs CS 150 - Fall 2000 - Sequential Logic Implementation - 72

Sequential Logic Implementation Summary z Models for representing sequential circuits y Abstraction of sequential

Sequential Logic Implementation Summary z Models for representing sequential circuits y Abstraction of sequential elements y Finite state machines and their state diagrams y Inputs/outputs y Mealy, Moore, and synchronous Mealy machines z Finite state machine design procedure y Deriving state diagram y Deriving state transition table y Determining next state and output functions y Implementing combinational logic z Implementation of sequential logic y State minimization y State assignment y Support in programmable logic devices CS 150 - Fall 2000 - Sequential Logic Implementation - 73