Sequential Circuits Latches FlipFlops Sequential Circuits Combinational Logic

Sequential Circuits: Latches & Flip-Flops

Sequential Circuits • Combinational Logic: – Output depends only on current input – Able to perform useful operations (add/subtract/multiply/encode/decode/ select[mux]/etc…) – Require cascading of many structures – Costly and inflexible 15 -Jan 22 Chapter 4: Sequential Circuits (4. 1 -- 4. 3) 2

Sequential Circuits (cont. ) • Sequential Logic: – Output depends not only on current input but also on past input values – Store information between operations – Need some type of memory (Register) to remember the past input values. (Commonly use D type Flip Flops as Registers) 15 -Jan 22 Chapter 4: Sequential Circuits (4. 1 -- 4. 3) 3

Define Schematic Terminology D(3: 0) 4 I/Ps O/Ps 4 P Dout(3: 0) 5 Not a short circuit! Signals merge into a Bus or Vector D(3) D(2) (P, Dout(3: 0)) D(3: 0) D(1) D(0) 15 -Jan 22 Chapter 4: Sequential Circuits (4. 1 -- 4. 3) 4

Sequential Circuits (cont. ) Information Storing Circuits – Registers(Flip Flops) 15 -Jan 22 Probably more than 1 bit if >2 states Timed “States” Chapter 4: Sequential Circuits (4. 1 -- 4. 3) 5

Sequential Logic: Concept • Sequential Logic circuits remember past inputs and past circuit state. • Outputs from the system are “fed back” as new inputs. • The storage elements are circuits that are capable of storing binary information: memory. 15 -Jan 22 Chapter 4: Sequential Circuits (4. 1 -- 4. 3) 6

Synchronous vs. Asynchronous machines There are two types of sequential circuits: • Synchronous sequential circuit: the behavior can be defined from knowledge of its signal at discrete instants of time. This type of circuits achieves synchronization by using a timing signal called the clock. • Asynchronous (fundamental mode) sequential circuit: the behavior is dependent on the order of input signal changes over continuous time, and output can change at any time (clockless). 15 -Jan 22 Chapter 4: Sequential Circuits (4. 1 -- 4. 3) 7

Clock Signal Rising Clock Edge Clock generator: Periodic train of clock pulses Different duty cycles 15 -Jan 22 Chapter 4: Sequential Circuits (4. 1 -- 4. 3) Falling Clock Edge 8

Circuits: Flip flops as state memory n The flip-flops receive their inputs from the combinational circuit and also from a clock signal with edges (rising or falling) that occur at fixed intervals of time, as shown in the timing diagram. 15 -Jan 22 Chapter 4: Sequential Circuits (4. 1 -- 4. 3) 9

Storing Elements Can’t change the stored value! Inverters Buffers 15 -Jan 22 Chapter 4: Sequential Circuits (4. 1 -- 4. 3) 10

SR latch (NOR version) -- SR: “set-reset”, bistable element with two extra inputs; note the “undefined” output for S=R=1. -- Reading the logic: § 15 -Jan 22 Q = (R+Q’)’; P = (S+Q)’ Chapter 4: Sequential Circuits (4. 1 -- 4. 3) Illegal state 11

R=S=1 ? ? • Illegal output, because – When S=R=1, both outputs go to zero. – If both inputs now go to 0, the state of the SR flip flop is depends on which input remains a 1 longer before making transition to 0. – Hence, “undefined” state. MUST be avoided. 15 -Jan 22 Chapter 4: Sequential Circuits (4. 1 -- 4. 3) 12

S’R’ Latch (NAND version) 0 S’ 1 R’ Q Q’ 1 0 S’ 0 0 1 1 R’ 0 1 Q Q’ 1 0 Set X Y NAND 00 1 01 1 10 1 11 0 15 -Jan 22 Chapter 4: Sequential Circuits (4. 1 -- 4. 3) 13

S’R’ Latch (NAND version) 1 S’ 1 R’ Q Q’ 1 0 S’ 0 0 1 1 R’ 0 1 Q Q’ 1 0 Set 1 0 Hold X Y NAND 00 1 01 1 10 1 11 0 15 -Jan 22 Chapter 4: Sequential Circuits (4. 1 -- 4. 3) 14

S’R’ Latch (NAND version) 1 S’ 0 R’ Q Q’ 0 1 S’ 0 0 1 1 R’ 0 1 Q Q’ 1 0 Set 0 1 Reset 1 0 Hold X Y NAND 00 1 01 1 10 1 11 0 15 -Jan 22 Chapter 4: Sequential Circuits (4. 1 -- 4. 3) 15

S’R’ Latch (NAND version) 1 S’ 1 R’ Q Q’ 0 1 S’ 0 0 1 1 R’ 0 1 Q Q’ 1 0 0 1 Set Reset Hold X Y NAND 00 1 01 1 10 1 11 0 15 -Jan 22 Chapter 4: Sequential Circuits (4. 1 -- 4. 3) 16

S’R’ Latch (NAND version) 0 S’ 0 R’ Q 1 Q’ 1 S’ 0 0 1 1 R’ 0 1 Q 1 1 0 Q’ 1 Disallowed 0 Set 1 Reset 0 Hold 1 Hold X Y NAND 00 1 01 1 10 1 11 0 15 -Jan 22 Chapter 4: Sequential Circuits (4. 1 -- 4. 3) 17

SR Latches 15 -Jan 22 Chapter 4: Sequential Circuits (4. 1 -- 4. 3) 18

SR Latch Simulation (Timing Diagram) 15 -Jan 22 Chapter 4: Sequential Circuits (4. 1 -- 4. 3) 19

SR Latch with Clock signal CLK Latch is sensitive to input changes ONLY when C=1 15 -Jan 22 Chapter 4: Sequential Circuits (4. 1 -- 4. 3) 20

SR Latch with Clock signal (cont. ) S S’ Q CLK Q’ R S R CLK S’ R’ 0 0 0 1 1 X X 15 -Jan 22 R’ 1 1 0 1 1 1 0 0 1 1 Q Q’ Q 0’ 0 1 1 Q 0’ Chapter 4: Sequential Circuits (4. 1 -- 4. 3) Store Reset Set Disallowed Store 21

D Latch • One way to eliminate the undesirable indeterminate state in the RS flip flop is to ensure that inputs S and R are never 1 simultaneously. This is done in the D latch: CLK 15 -Jan 22 Chapter 4: Sequential Circuits (4. 1 -- 4. 3) 22

D Latch (cont. ) D S S’ Q CLK Q’ R D 0 1 X 15 -Jan 22 CLK 1 1 0 Q Q’ 0 1 1 0 Q 0’ R’ S R CLK Q Q’ 0 0 1 1 X Q 0’ Store 1 Reset 0 Set 1 Disallowed Q 0’ Store 0 1 1 1 X 0 Q 0 0 1 1 Q 0 Chapter 4: Sequential Circuits (4. 1 -- 4. 3) 23

Latches: Behaviour & Issues • Level triggered • Latches are “transparent” (= any change on the inputs is seen at the outputs immediately). • This causes synchronization problems! (not recommended for use in synchronous designs) • Solution: use latches to create flip-flops that can respond (update) ONLY on SPECIFIC times (instead of ANY time). 15 -Jan 22 Chapter 4: Sequential Circuits (4. 1 -- 4. 3) 24

Alternatives in FF choice • Edge triggered (rising or falling edge of clk) used in synchronous design • Various types exist: – RS –D – JK 15 -Jan 22 Chapter 4: Sequential Circuits (4. 1 -- 4. 3) 25

SR Flip Flop CLK CLK Master Slave CLK – Enables edge-triggered behavior –This 15 -Jan 22 is NOT a latch (even though it is built from latches Chapter 4: Sequential Circuits (4. 1 -- 4. 3) 26

SR Flip Flop (contd. ) S R CLK Q Q’ 0 0 0 1 1 X X 0 CLK 15 -Jan 22 Q 0 0 1 1 Q 0’ 1 0 1 Q 0’ Store Reset Set Disallowed Store CLK • When C=1, master is enabled and stores new data, slave stores old data. • When C=0, master’s state passes to enabled slave (Q=Y), master not sensitive to new data (disabled). CLK Chapter 4: Sequential Circuits (4. 1 -- 4. 3) 27

Master-Slave J-K Flip-Flop CLK CLK 15 -Jan 22 Chapter 4: Sequential Circuits (4. 1 -- 4. 3) 28

Positive Edge-triggered D Flip. Flops • Attach level-triggered D latch to level-triggered SR latch, using complemented clocks. • D-Type Positive Edge-Triggered Flip-Flop: CLK 15 -Jan 22 CLK Chapter 4: Sequential Circuits (4. 1 -- 4. 3) 29

Positive Edge-Triggered J-K Flip-Flop CLK CLK 15 -Jan 22 Chapter 4: Sequential Circuits (4. 1 -- 4. 3) 30