Seminar by Prof Dr Jos Camargo da Costa
Seminar by Prof. Dr. José Camargo da Costa November 22, 2002, ENE, Un. B, Brasilia Reiner Hartenstein* Kaiserslautern University of Technology (TU Kaiserslautern) *) IEEE fellow Data-stream-based Computing, Enabling Technology for Reconfigurable Computing Friday, November 22, 2002, 17. 00 hrs.
>> Microelectronics History TU Kaiserslautern • Microelectronics History • fine grain and coarse grain Morphware • Anti Matter of Computing • Anti Machine and its Resources • Problems to be solved http: //www. uni-kl. de © 2002, reiner@hartenstein. de 2 http: //hartenstein. de
The History of Paradigm Shifts TU Kaiserslautern © 2002, reiner@hartenstein. de ASICs, accel’s 1977 3 1997 d e h is 9 l b Pu 198 in e custom LSI, MSI 2007 ar hw 1957 1987 rp 1967 µproc. , memory mo TTL “The Programmable System-on-a-Chip is the next wave“ 2 nd Design Crisis standard 1 st Design Crisis e v a W s ’ o Makimot “Mainstream Silicon Application is switching every 10 Years” http: //hartenstein. de
The Impact of Makimoto’s Paradigm Shifts TU Kaiserslautern Software Industry’s Secret of Success Personalization (CAD) before fabrication standard ASICs, accel’s 1977 1997 2007 le ab ur © 2002, reiner@hartenstein. de 1987 fig custom LSI, MSI structural personalization: RAM-based before run time n co 1957 Procedural personalization via RAM-based Machine Paradigm re 1967 Repeat Success Story by new Machine Paradigm ! µproc. , memory TTL Dr. Makimoto: FPL 2000 keynote 4 http: //hartenstein. de
The EDA Industry Revolution “Thenext Programmable System-on-a-Chip is the next wave“ TU Kaiserslautern Makimoto’s 3 rd wave Von Neumann does not support Morphware: EDA industry paradigm switching every 7 years [Hartenstein] 1999 [Keutzer / Newton] Mc. Kinsey Curves 1992 Synthesis (HDLs): Cadence, Synopsys. . . 1985 1978 (Co-) Compilation: data-stream-based DPAs Schematics entry: Daisy, Mentor, Valid. . . Transistor entry: Applicon, Calma, CV. . . © 2002, reiner@hartenstein. de 5 http: //hartenstein. de
Ubiquitous embedded systems TU Kaiserslautern Embedded systems means: 20 billion µprocessors (2001) • hardware / software co-design > 90% in embedded systems 10 times more programmers will write embedded applications than computer software by 2010 That’s where our graduates will go © 2002, reiner@hartenstein. de 6 • configware / software co-design • hardware / configware / software co-design http: //hartenstein. de
Embedded Systems Requirement: TU Kaiserslautern Hardware/Configware and Software as Alternatives Algorithm partitioning Hardware, Configware Software Hardw/Configw Software only Softwareonly & Hardw/Configw © 2002, reiner@hartenstein. de 7 http: //hartenstein. de
>> fine grain and coarse grain Morphware TU Kaiserslautern • Microelectronics History • fine grain and coarse grain Morphware • Anti Matter of Computing • Anti Machine and its Resources • Problems to be solved http: //www. uni-kl. de © 2002, reiner@hartenstein. de 8 http: //hartenstein. de
Top 4 FPGA Manufacturers 2000 TU Kaiserslautern 12 12 16 no. of masks 20 26 28 30 Lattice 15% cost / mio § 4 >30 NRE and mask cost [dataquest] Actel 6% Xilinx 42% 3 . Altera 37% 2 mask set cost [e. ASIC] 0. 8 0. 6 0. 35 0. 25 0. 18 0. 15 0. 13 0. 1 Top 4 PLD Manufacturers 2000 • [Dataquest] > $7 billion by 2003. 1 • FPGAs going into every type of application – also So. C 0. 07 feature size You do not neet specific silicon ! © 2002, reiner@hartenstein. de total: $3. 7 Bio 9 • fastest growing segment of semiconductor market http: //hartenstein. de
Configware and EDA as the Key Enabler TU Kaiserslautern • Growing no. of independent configware houses (soft IP core vendors) and design services provide libraries of "pre-fabricated" re-usable IP cores • Emerging separate EDA software market FPGA synthesis [2001: Dataquest]: • Synplicity 57%, • Mentor 37%, • Synopsys 7% © 2002, reiner@hartenstein. de 10 http: //hartenstein. de
Throughput vs. Efficiency TU Kaiserslautern MOPS / m. W 1000 L 100 d r a h 10 stan 0. 01 0. 001 a ur fig ble )* g n i ut p com ic g o l ) le b a SP r D u s A fig n ors o r. DP s c s e oce r s (r p A et s FPG n o i ssor e t c c o r ru icrop m d r inst da 0. 1 Wiring by abutment: 32 Bit example ed r i w n co e r ( 1 2 © 2002, reiner@hartenstein. de area used by application T. Claasen et al. : ISSCC 1999 *) R. Hartenstein: ISIS 1997 1 0. 5 0. 25 11 L S S L L L S L 1 Bit CLB L resources needed for reconfigurability 0. 13 0. 1 0, 07 µ feature size http: //hartenstein. de
Commercial r. DPAs TU Kaiserslautern XPU family (IP cores): PACT AG. , Munich http: //pactcorp. com ACM: Quicksilver Tech © 2002, reiner@hartenstein. de XPU 128 12 http: //hartenstein. de
SNN filter Kress. Array Mapping Example TU Kaiserslautern http: //kressarray. de rout thru only data streams array size: 10 x 16 = 160 r. DPUs © 2002, reiner@hartenstein. de backbus connect 13 not used http: //hartenstein. de
TU Kaiserslautern Kress. Array Family generic Fabrics: a few examples Select mode, Select number, width of NNports 16 8 32 Function Repertory + 24 2 r. DPU 4 select Nearest Neighbour (NN) Interconnect: an example routthrough only more NNports: rich Rout Resources rout-through and function Examples of 2 nd Level Interconnect: layouted over r. DPU cell - no separate routing areas ! http: //kressarray. de © 2002, reiner@hartenstein. de 14 http: //hartenstein. de
Antimatter of Computing is available TU Kaiserslautern • Using FPGAs (fine grain morphware) has been just Logic Synthesis on a strange platform • Coarse Grain r. DPAs (Reconfigurable Computing): a fundamental Paradigm Shift • up several abstraction levels a D • © 2002, reiner@hartenstein. de m o C ed as b am e r t s ta 15 g n i put http: //hartenstein. de
>> Anti Matter of Computing TU Kaiserslautern • Microelectronics History • fine grain and coarse grain Morphware • Anti Matter of Computing • Anti Machine and its Resources • Problems to be solved http: //www. uni-kl. de © 2002, reiner@hartenstein. de 16 http: //hartenstein. de
The anti universe TU Kaiserslautern • Paul Dirac predicted a complete anti universe consisting of antimatter • “There are regions in the universe, which consist of antimatter. . . • . . But there asymmetries” • when a particle hits antiparticle, both are converted into energy: Annihilation • We are not aware, that there is a new area in computing sciences , which consists of antimatter of computing • Reconfigurable Computing is made from this antimatter: data-stream-based computing © 2002, reiner@hartenstein. de 17 http: //hartenstein. de
anti particles TU Kaiserslautern • 1928: Paul Dirac: „there should be an anti electron having positive charge“ (Nobel price 1933) • 1932: Carl David Anderson detected this „positron“ in cosmic radiation (Nobel price 1936) hydrogen • 1954: new accelerators: cyclotron, like Berkeley‘s Bevatron anti hydrogen • 1955 Owen Chamberlain et al. create anti proton on Bevatron • 1956: anti neutron created on Bevatron • 1965: creation of a deuterium anti nucleus at CERN • 1995: hydrogen anti atom created at CERN – by forcing positron and anti proton to merge by very low energy. © 2002, reiner@hartenstein. de 18 http: //hartenstein. de
Matter & Antimatter: Atom and Anti Atom TU Kaiserslautern - + Anti Matter machine paradigm: Anti Atom g n i n n i p s n o r t c e l E - The World of Matter machine paradigm: the Atom P © 2002, reiner@hartenstein. de 19 + g n i n pin s n o r t i s o http: //hartenstein. de
Matter & Antimatter of Informatics : Machine and Anti Machine TU Kaiserslautern CPU - + m a e r t s n o i t c u r t s in g n i n n i p s Anti Machine paradigm 1936 1946 1971 1979 1990 1995 Machine paradigm: „von Neumann“ 1 st electronic computer (Konrad Zuse) v. N. machine paradigm 1 st microprocessor (Ted Hoff) „data streams“ (systolic array: Kung / Leiserson) anti machine paradigm published r. DPA / DPSS (supersystolic: Rainer Kress) novel compilation techniques DPU + - ng i n n i p s m a ts availab e r t s le 20 data http: //hartenstein. de © 2002, reiner@hartenstein. de all ingred ien
Matter vs. antimatter: CPU vs. DPU + Data Path instruction sequencer instruction stream © 2002, reiner@hartenstein. de 21 DPU - + + + - e r a es e ri r e et h t m m y as data streams CPU + + TU Kaiserslautern DPU Data Path Unit http: //hartenstein. de
heavy anti atoms: DPA = DPU array coherent data streams spinning around TU Kaiserslautern + DPU - DPU DPU DPU DPA + + © 2002, reiner@hartenstein. de + + + - - - 22 - + DPA + - + http: //hartenstein. de
Parallelism by Concurrency independent instruction streams difficult. . . TU Kaiserslautern + + - - © 2002, reiner@hartenstein. de + + - + 23 - + http: //hartenstein. de
>> Anti Machine and its Resources TU Kaiserslautern • Microelectronics History • fine grain and coarse grain Morphware • Anti Matter of Computing • Anti Machine and its Resources • Problems to be solved http: //www. uni-kl. de © 2002, reiner@hartenstein. de 24 http: //hartenstein. de
Dichotomy of machine paradigms TU Kaiserslautern M as. M M address generator instruction stream CPU DPU instruction sequencer © 2002, reiner@hartenstein. de M M M M data streams data stream (r) DPU (r)DPU e r a es or i e r r t e e th m m y (r)DPU Array as (r)DPA 25 http: //hartenstein. de
Terminology: DPU versus CPU. . . TU Kaiserslautern • • • DPU: data path unit DPA: DPU array GA: gate array r. DPU: reconfigurable DPU r. DPA: reconfigurable DPA r. GA: reconfigurable GA • DPU is no CPU: there is nothing central - like in a DPA © 2002, reiner@hartenstein. de 26 r DPA r DPU CPU DPU instruction sequencer http: //hartenstein. de
TU Kaiserslautern Terminology: Digital System Platforms clearly distinguished source running on it platform hardware (not running on it) fine grain r. GA (FPGA) morphware coarse r. DPU, r. DPA grain reconfigurable data stream processor (hardwired) instruction stream processor © 2002, reiner@hartenstein. de machine paradigm configware flowware & configware flowware software 27 none anti machine von Neumann machine http: //hartenstein. de
flowware defines. . TU Kaiserslautern time x x x DPA time | x x x - time - - x x x - - - x x x | | | x x x time x x x | port # 28 port # - - - x x x - - flowware manipulates the data counter(s). . . software manipulates the program counter © 2002, reiner@hartenstein. de | input data streams | | . . . which data item at which time at which port x x x port # output data streams | x x x http: //hartenstein. de
Configware / Flowware Compilation TU Kaiserslautern M M high level source program data streams M M M © 2002, reiner@hartenstein. de M M M r. Data Path Array mapper M r. DPA wrapper intermediate configware M M M as. M scheduler address generator 29 flowware data sequencer http: //hartenstein. de
. . . for a Stream-based Soft Machine TU Kaiserslautern Memory (data memory) Compiler “instructions” Scheduler r. DPA memory bank . . . memory bank Sequencers (data stream generator ) © 2002, reiner@hartenstein. de 30 http: //hartenstein. de
![*> Declarations South. West. Scan is TU Kaiserslautern loop 8 times until [1, *]](http://slidetodoc.com/presentation_image_h/300ecd03bd6f709f98474ffec992f5fe/image-31.jpg "*> Declarations South. West. Scan is TU Kaiserslautern loop 8 times until [1, *]")
*> Declarations South. West. Scan is TU Kaiserslautern loop 8 times until [1, *] step by [-1, 1] endloop end South. West. Scan; JPEG zigzag scan pattern Half. Zig. Zag; Flowware language example South. West. Scan (Mo. PL) The same langua uturn (Half. Zig. Zag) ge principles goto Pix. Map[1, 1] South. Scan is step by [0, 1] end. South. Scan; North. East. Scan is loop 8 times until [*, 1] step by [1, -1] x y data. Half. Zig. Zag counter data counter endloop end North. East. Scan; East. Scan is step by [1, 0] end East. Scan; endloop end Half. Zig. Zag; © 2002, reiner@hartenstein. de 31 Half. Zig. Zag is East. Scan loop 3 times South. West. Scan South. Scan North. East. Scan http: //hartenstein. de
TU Kaiserslautern GAG Slider Model ceiling sliders floor GAG B 0 DA [ B 0 Generic Address Generator L 0 ] DA L 0 [ © 2002, reiner@hartenstein. de ] 32 http: //hartenstein. de
GAG Slider Operation Demo Example TU Kaiserslautern address slid floor F er B 0 flo o rs lid e r cei ling © 2002, reiner@hartenstein. de 33 http: //hartenstein. de
GAG Complex Sequencer Implementation TU Kaiserslautern GAG L 0 DA B 0 Limit Slider Address Stepper A VLIW stack L 0 DA B 0 Base Slider Limit Slider Address Stepper GAG A L 0 DA B 0 Limit Slider GAU Address Stepper A GAU SDS Base Slider GAG Generic Addressing Unit © 2002, reiner@hartenstein. de Base Slider 34 all `been published in 1990 http: //hartenstein. de
Generic Sequence Examples L 0 DA B 0 TU Kaiserslautern atomic scan linear scan a) Address Stepper Limit Slider video scan b) A Base Slider GAU -90º rotated video scan c) -45º rotated (mirx (v scan)) until sheared video scan non-rectangular video scan zigzag video scan d) e) f) g) spiral scan feed-back-driven scans perfect shuffle © 2002, reiner@hartenstein. de 35 d e h s 0 i l b u p 9 9 1 in http: //hartenstein. de
TU Kaiserslautern Storage scheme optimization: scanline unrolling Mo. M anti machine architecture w/r r r Bank a r r r Bank b r r r Bank a final design after inner scan line loop unrolling after scan line unrolling hardw. level access optim. initial design © 2002, reiner@hartenstein. de 36 http: //hartenstein. de
>> Problems to be solved TU Kaiserslautern • Microelectronics History • fine grain and coarse grain Morphware • Anti Matter of Computing • Anti Machine and its Resources • Problems to be solved http: //www. uni-kl. de © 2002, reiner@hartenstein. de 37 http: //hartenstein. de
What is the trend ? TU Kaiserslautern • Data-stream-based Computing • v. N is needed for embedded systems, OS, compilers, is heading for mainstream Sauerkraut software, nonperformance-critical applications, – 1979 „data streams“ (Kung / Leiserson) – 1997 SCCC (LANL) Streams-C Configurabble others …. • v. N is obsolete for massive parallelism, except some special application areas • Anti machine is the way to go for massive parallelism, also data-intensive applications Computing –SCORE (UCB) Stream Computations Organized for Reconfigurable Execution –ASPRC (UCB) Adapting Software Pipelining for Reconfigurable Computing – 2000 Bee (UCB), . . . –Most stream-based multimedia systems, etc. –Many other areas. . • Morphware is the way for high performance with short product life cycles, unstable standards © 2002, reiner@hartenstein. de 38 http: //hartenstein. de
Conclusion: all knowledge needed is available TU Kaiserslautern • machine paradigm courses / embedded tutorials: • DATE. Munich, 2001 • ASP-DAC, Yokohama, 2001 • SBCCI, Brasilia, 2001 • languages • hw / sw partitioning methodology • compilation techniques • anti architectural resources • sequencing methodology: hw & sw full day courses: Univ. Montpellier 1998 Nokia / Univ. Tampere, Finland, 2002 CNRS Paris France, 2002 Un. B, Brasilia, 2002 • • 10 keynotes 2001 / 2002 5 invited talks 2001 / 2002 • parallel memory IP core and module generator vendors • anything else needed © 2002, reiner@hartenstein. de 39 http: //hartenstein. de
Main problems to be solved TU Kaiserslautern • Lack of qualified users and implementers • Each programmer should have qualified awareness on dichotomy and morphware computing systolic arrays in space in time etc. migration by re-timing and other transformations • curricular innovations are urgently needed © 2002, reiner@hartenstein. de this dichotomy is completely ignored by our CS curricula 40 http: //hartenstein. de
CS education. . . TU Kaiserslautern Configware / Software Co-Design? Hardware / Software Co-Design? An hardware person procedural nih ila tio n? structural © 2002, reiner@hartenstein. de 41 software person http: //hartenstein. de
Annihilation? TU Kaiserslautern as h + cr - avoidable by careful methodology © 2002, reiner@hartenstein. de + 42 http: //hartenstein. de
TU Kaiserslautern However, CS Education …. … is basedcurrent on the Submarine Model This model disables. . . Algorithm Brain usage: procedural-only re a w t Sof procedural high level Programming Language Assembly Language Hardware invisible: under the surface Hardware shy Software Faculty Colleagues away from the Paradigm Shift: their Brain hurts? - can’t be: has been amputated Halfreiner@hartenstein. de ©this 2002, 43 http: //hartenstein. de
Hardware and Software as Alternatives TU Kaiserslautern procedural structural Algorithm partitioning Brain Usage: both Hemispheres Hardware, Configware Software Hardw/Configw Software only Softwareonly & Hardw/Configw © 2002, reiner@hartenstein. de 44 http: //hartenstein. de
The Dominance of the Submarine Model. . . TU Kaiserslautern (procedural) structurally disabled Hardware . . . indicates, that our CS education system produces zillions of mentally disabled Persons It‘s time to attack the software faculty dictatorship. Get involved ! © 2002, reiner@hartenstein. de … completely disabled to cope with solutions other than software only 45 http: //hartenstein. de
TU Kaiserslautern Antimatter Search ? in EE & CS we do not need to search Antimatter Search © 2002, reiner@hartenstein. de 46 http: //hartenstein. de
>>> thank you TU Kaiserslautern thank you for your patience © 2002, reiner@hartenstein. de 47 http: //hartenstein. de
>>> END TU Kaiserslautern END © 2002, reiner@hartenstein. de 48 http: //hartenstein. de
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