Sector Logic Board The ATLAS Muon Trigger Sector
Sector Logic Board The ATLAS Muon Trigger Sector Logic/RX Data Acquisition Board Author: Federico Spila INFN Rome Twepp – September, 4, 2007
1/13 LVL 1 Muon Barrel Trigger SIDE C HV side 3 Planes of RPC Detectors Outer Middle-pivot Inner SIDE A 3 Planes of RPC RO Side Each with 6 or 7 Chambers Trigger Tower 16 Sectors on the Azimuthal Plane 32 6 Geometrical or 7 Trigger. Sectors Towers each Trigger 64 on Trigger Sectors. Sector Twepp – September, 4, 2007
2/13 Lvl 1 Trigger Electronics Low Pt PAD BOX ON Detector Electronics Off Detector Electronics • Read-Out Data High Pt PAD BOX • Implement Event Building To Sector Logic… • Send Output Data to ROD …From PAD • Read Trigger Data • Implement Trigger algorithm • Send Output Data to MUCTPI Twepp – September, 4, 2007
3/13 VME Crates MUCTPI-Interface USA 15 Room 16 VME Crates Sector Logic Read-Out Data: Backplane Connection MUCTPI SCSI Connectors Each takes data from VME CRATE 2 Geometrical Sectors Each takes data from 2 Trigger Sectors Central Trigger Optical receivers Processor ROD Sector Logic MUCTPI - Interface VME CRATE Trigger Data are LVDS Parallel Bus In Total 64 Sector Logic Boards Trigger Data L 1 Barrel Trigger L 1 End-Cap Trigger External cables -> LVDS BUS …To MUCTPI board Twepp – September, 4, 2007
4/13 ROD-BUS SL <-> ROD Real ROD Block • Sends Read-Out Data MUCTPI - Interface Sector Logic ROD Sector Logic 32 1. ROD MUCTPI-Interface Modules as the • Receives TTC Signals ATLAS Geometrical Sectors BUS mounted on a 2. ROD Sector Logic VME Back-Panel Each ROD reads 2 Sector Logics 3. ROD MUCTPI - Interface Sector Logic Sector ROD Logic Sector Logic MUCTPI - Interface VME Crate ROD Block SL <-> MUCTPI-Interface 4. Sector Logic • Sends Trigger Data 5. MUCTPI-Interface • Receives Service Signals Twepp – September, 4, 2007
5/13 Sector Logic Schema 4 G 2 Link RX Cards Xilinx Virtex 2 XC 2 V 1000 Xilinx Virtex 2 XC 2 V 2000 Serializer chip VME Communication JTAG Other All 40 Sector bit. Services TTLLogic input features -> 8 bit LVDS output stream Each with 2 Optical link receivers Speedrate 240 Mbyte/s VME FPGA SL FPGA Twepp – September, 4, 2007
6/13 VME FPGA Firmware VME FPGA VME 64 x Client Protocol 8 Registers 1 FIFO SL FPGA 44 Registers 12 FIFOs SBC (VME Server) VME BUS Custom Master-Slave Protocol All Registers & FIFOs 32 bit lenght Twepp – September, 4, 2007 7 bit Address
7/13 Master-Slave Protocol 24 bit bidirectional VME SL External FIFO Access 16 bit Data 7 bit Address Configuration signals of Link Cards & Serializer JTAG signals 1 bit R/W VME FPGA is the Master Transmit first the low significant 2 bytes, after the more significant 2 bytes Twepp – September, 4, 2007
8/13 SL FPGA Firmware SL FPGA Link 0 -1 CLOCK DISTRIBUTION …To VME FPGA READ-OUT TRIGGER VME ACCESS LOGIC …To Serializer Link 2 -3 Link 4 -5 …To MUCTPI-I Link 6 -7 Twepp – September, 4, 2007
9/13 Trigger Logic Link 0 -1 Link 2 -3 Link 4 -5 BC 1: When a MUON candidate is detected Solves the PAD Overlap The. Trigger Sectoroutput Logic receives Trigger data 32 word From 1 or more PADs 16 bit Trigger Word • Information about the BC 2: 2 Muon Candidates Detects • BC-ID the first High Pt muon • BC-ID using a • 8 x 7 Matrix comparator Overlap • FLAG “More than 2 candidates” • Threshold • ROI TRIGGER LOGIC Total processing Time: BC 3: Detects the second High Pt muon 5 BC (125 ns) using a 8 x 6 Matrix comparator …To MUCTPI-I Link 6 -7 Store Trigger Data in an internal FIFO Used by the Read-Out Logic Twepp – September, 4, 2007
10/13 Read-Out Logic When a L 1 A Signal arrives from TTC The Sector Logic receives Read-Out data 16 bit Pad Frame From all the PADs L 1 -ID & BC-ID are syncronized PAD Header Fifo 0 Fifo 1 Link 0 -1 Fifo 2 Link 2 -3 Fifo 4 Fifo 5 Fifo 6 Produces the Output. Data Packet … 32 bit SL Frame Event Building READ-OUT LOGIC FIFO OUT Pad 1 Frame Serializer Pad 2 Frame …To Serializer Pad 3 Frame Pad 4 Frame Pad 5 Frame FIFO Pad 6 Frame Trigger Check Frame Link 4 -5 Link 6 -7 Fifo Trig Data SL Header PAD Footer Pad 0 Frame VME SL Footer 80 MHz Clk Twepp – September, 4, 2007
11/13 VME SL Logic GENERAL PURPOSE BOARD for Testing • PADs • Sector Logics • RODs • MUCTPIs …To VME FPGA VME ACCESS Master-Slave Custom Protocol - Write input FIFOs simulating PADs - Write Timing signals simulating the TTC - Write the Output Data directly to ROD - Write the Output Data directly to MUCTPI - Mounting G 2 Link TX, we can emulate the PAD Twepp – September, 4, 2007
TTC Input Clock FIFO Clk 12/13 Timing Logic Link 0 FIFO 0 Link 1 FIFO 1 VME Clock LOCAL Serializer Clock. Clk VME ACCESS VME Link 2 Link 3 FIFO 2 TRIGGER FIFO 3 Link 4 FIFO 4 Link 5 FIFO 5 Link 6 FIFO OUT SERDES READ-OUT MUCTPI Event Building Clk Twepp – September, 4, 2007
13/13 Conclusions & M 4 RUN DAQ Software SBC MUCTPI-I ROD SL SL ROD SL MUCTPI-I VME See Cosmic Muon events in Read-Out Data SL MUCTPI-I SBC VME All The L 1 -ID & BC-ID of the 2 Sectors are syncronized Sector 5 Side A Sector 5 Side C M 4 Integrated Cosmic Run L 1 Trigger End-Cap Future: L 1 Trigger we will test and install the other 60 SL boards CALO MUCTPI Central Trigger Processor Twepp – September, 4, 2007
THE END Twepp – September, 4, 2007
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