Section B A StepByStep Description of the Synplicity
Section B A Step-By-Step Description of the Synplicity Flow Andy Miller © Copyright 2000 Xilinx - All Rights Reserved www. xilinx. com
Synplicity Flow - Start New Project Andy Miller © Copyright 2000 Xilinx - All Rights Reserved www. xilinx. com
Synplicity Flow - Start New Project 1 1 Select. . . File->New 2 Set a New file location to be your Sys. Gen working directory Click “OK” 3 4 Double-click on “Project File” to accept it. 4 3 2 Andy Miller © Copyright 2000 Xilinx - All Rights Reserved www. xilinx. com
Synplicity Flow - Add Sys. Gen Files Now we add the System Generator files to the new Synplicity Project. 1 Select. . File->Add File. 2 Note that the default HDL is Verilog. Click on the down arrow and select *. VHD. 1 3 Because you completed Step 2 on the previous page, a list of Sys. Gen VHD files will appear in this window. 4 3 2 to where you told Sys. Gen to put them with the Sys. Gen GUI. 5 Select the “Add All” button and 5 Andy Miller © Copyright 2000 Xilinx - All Rights Reserved 4 If they did not, then navigate watch them appear in the lower window. www. xilinx. com
Synplicity Flow - Add Sys. Gen Files Now we add the System Generator VHDL descriptions of any module that cannot be mapped to a CORE Generator. TM core. 1 These files are stored in: $Matlab 12/toolbox/xilinx/sysgen/vhdl 2 Select the “Add All” button - this it is the quickest way to get all the components you need in one go! NOTE: You will also see components that you do not need; the synthesis tool ignores everything except the FIFO core, which I will mention on the next foil. Andy Miller © Copyright 2000 Xilinx - All Rights Reserved www. xilinx. com
Synplicity Flow - Order the Files 1 2 Note that you must move the conv_pkg using the same click and drag technique so that it occupies the second position in the list. …. . Sometimes I wonder if synthesis really is easier! Andy Miller © Copyright 2000 Xilinx - All Rights Reserved www. xilinx. com
Synplicity Flow - Compile the design 1 2 Select RUN -> Compile to see if the synthesis tool is happy with the files and their order. At this stage, you may get an ERROR from the xlfifo_core. vhd file if you forgot to delete it. Simply delete it and hit F 7, or repeat Step 1. Andy Miller © Copyright 2000 Xilinx - All Rights Reserved www. xilinx. com
Synplicity Flow - Select Device 1 Now you are almost ready to synthesize the design; you just need to choose the target device and identify where the output files will be placed. Select “Impl Options. ” 2 Choose the target family. (Note that only Xilinx Virtex/E/II and Xilinx Spartan-II will work. ) 3 Choose the part. 4 Choose the speed grade. (Note -6 = slowest; -8 = fastest) 5 Choose the package. 6 Select the Options/Constraints tab. Andy Miller © Copyright 2000 Xilinx - All Rights Reserved www. xilinx. com
Synplicity Flow - Target the Output 1 Select to where the target files are going to be written. 2 Andy Miller © Copyright 2000 Xilinx - All Rights Reserved www. xilinx. com Select “OK. ”
Synplicity Flow - Synthesize the design 1 Andy Miller © Copyright 2000 Xilinx - All Rights Reserved www. xilinx. com Now Synthesize the design by hitting the RUN button.
- Watch how it speeds along : o) As Synplicity is running, it indicates what it is doing. It can sometimes be in the mapping phase for a long time. Andy Miller © Copyright 2000 Xilinx - All Rights Reserved www. xilinx. com
Synplicity Flow - View the RTL diagram When Synplicity has completed the design, click on this icon to view the RTL (Register Transfer Level) view of the design. This is a logical representation of the design, and there is normally a 1 -to-1 correlation between the blocks within the Simulink diagram and the Sythensis diagram. Andy Miller © Copyright 2000 Xilinx - All Rights Reserved www. xilinx. com
View the Technology Mapped Result Now click on this icon to see how Synplicity has actually mapped the design. It will be at this stage that you can sometimes notice the effect of NOT choosing to use CORE Generator Cores. If you use COREGen cores, you will not be able to navigate into the hierarchy using this icon. Xlmult: This is a COREGen Core, and it cannot be traversed with the hierarchy viewer because the EDIF has been created by CORE Generator. The Synthesis tool treats this block as a black box. Andy Miller © Copyright 2000 Xilinx - All Rights Reserved www. xilinx. com
View the Technology Mapped Result Now click on this icon to see how Synplicity has actually mapped the design. At this stage, you can also sometimes notice the effect of NOT choosing to use CORE Genenerator Cores. If you use COREGen cores, you will not be able to navigate into the hierarchy using this icon. (Press your “Page Down” key to end the presentation. ) www. xilinx. com
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