Scan Chain Reorder SyingJyan Wang Department of Computer

Scan Chain Reorder Sying-Jyan Wang Department of Computer Science National Chung-Hsing University NCHUCS 1

Outline o o o Overview Scan chain order: does it matter? Cluster-based reordering for lowpower BIST Experimental results Future work NCHUCS 2

Outline ■ o o Overview Scan chain order: does it matter? Cluster-based reordering for lowpower BIST Experimental results Future work NCHUCS 3

Digital Testing o o o To detect manufacturing defects Apply test patterns and observe output responses Test patterns generated for targeted fault models NCHUCS 4

Scenario for Manufacture Test TEST VECTORS … MANUFACTURED CIRCUIT … CORRECT RESPONSES COMPARATOR NCHUCS CIRCUIT RESPONSE PASS/FAIL 5

Scan Test (1) o o o A structural design-for-testability technique Storage elements are not directly accessible Scan test provides an easy way for test access n n Apply test patterns to circuit under test (CUT) Read output responses from CUT NCHUCS 6

Scan Test (2) o Sequential circuit n FFs are neither controllable nor observable Primary Input Combinational Logic Primary Output F F NCHUCS 7

Scan Test (3) o Normal signal path: parallel load Primary Input Combinational Logic Primary Output F F NCHUCS 8

Scan Test (4) o In scan mode: a shift register Primary Input Combinational Logic Primary Output Scan out (SO) F F Scan in (SI) NCHUCS 9

Scan Test (5) o To enable scan test n n o Each scan cell has two inputs o Normal input o Scan input All scan cells are connected into a shift register (scan chain) Turn a sequential test into a combinational one n n Apply test patterns directly Observe test results directly NCHUCS 10

Scan Chain o o o Normally constructed when placement and routing are done The order does not matter Find out the shortest scan chain order n n Traveling salesman problem (TSP) Asymmetric TSP (ATSP) o n SI and SO of a scan cell are not at the same location NP-complete NCHUCS 11

Outline o ■ o o o Overview Scan chain order: does it matter? Cluster-based reordering for lowpower BIST Experimental results Future work NCHUCS 12

Scan Test for Stuck-at Faults o Order does not matter As long as we can scan in test patterns and scan out test responses n 0 1 1 0 CUT 1010 1 0 1100 NCHUCS 1 0 13

Minimum Wirelength Routing o Use a TSP/ATSP solver n o Slow Wirelength can be 10 x with random order NCHUCS 14

Low-Power Testing o o A great concern in recent years Need to reduce signal transitions n n o The source of dynamic power in CMOS Usually the dominant factor Reorder scan chain to reduce switching activity 1010 1 1100 0 1 1 transition only 3 transitions NCHUCS 15

Delay Testing (1) o Require two-pattern tests n n o First pattern: initialization Second pattern: launch transition Delay test with simple scan chain n n Broadside o The output response of the 1 st pattern are captured in the scan chain and become the 2 nd pattern Skewed load o The 2 nd pattern is the result of 1 -bit shift of the 1 st pattern NCHUCS 16

Delay Test (2) o Broadside test n Eg. Apply v 1=(1010), v 2=(0100) Primary Input Combinational Logic 1 0 0 Primary Output F F NCHUCS 17

Delay Test (3) o Skewed load n Not all test pairs possible 2 n 2 n possible 2 -pattern combinations Only 2 2 n possible with single scan chain o o n 1010 0110 Reorder scan chain to achieve higher fault coverage 1 0 NOT POSSIBLE!! NCHUCS 1100 1 0 0 1 1 0 18

Hold Time Violation o Not enough propagation delay between adjacent flip-flops in a sequential circuit n o Double latching Possible solution n Reorder scan cells to introduce extra delay NCHUCS 19

Outline o o ■ o o Overview Scan chain order: does it matter? Cluster-based reordering for lower-power BIST Experimental results Future work NCHUCS 20

Overview o o Goal: Reduce BIST power Approach n n Include a smoother to reduce switching activity in test pattern generator (TPG) Use scan chain reordering to recover lost fault coverage o o Simple reordering algorithm Wirelength should not increase too much NCHUCS 21

Overall Architecture Single scan chain PRPG Smoother Internal scan chain TPG multiple scan chain P R P G ORA CUT P h a s e s h i f t e r NCHUCS Smoother Internal scan chain 1 Smoother Internal scan chain 2 . . Smoother . . O R A Internal scan chain k 22

Smoother 4 -state (2 bit) smoother n-state smoother 8 -state (3 bit) smoother 1/1 1/0 1/1 0/1 S 5 S 0 0/1 1/1 0/0 S 2 1/0 S 4 S 0 0/0 0/1 0/0 S 0 1/1 S 2 1/0 Sn/2 S 1 S 3 0/1 S 6 0/0 1/1 . . . 1/0 1/1 0/0 0/1 . . . 1/0 0/1 1/0 0/0 Sn/2– 1 1/1 0/1 1/0 1/1 Sn– 1 S 3 S 7 1/0 NCHUCS 23

A Simple Implementation of the n-state smother in u C 0 C Divide-by-n/2 Up-Down Counter d NCHUCS q T q 24

Estimation of Power Reduction o Probability of signal transition of an nstate smoother n o Compute from Markov chain model Estimation of dynamic power n n 2 -bit (4 -state ) smoother: 1/3 3 -bit (8 -state) smoother: 1/10 NCHUCS 25

Fault Coverage o Smoothed patterns are less random n May create repeated patterns and reduce fault coverage 10100101100 PRPG 2 -bit smoother 000000011110000 3 -bit smoother 00000000 Required test cube: Reorder scan chain: xxxxx 01 xxxxx 0 x 1 xxxxxxx NO MATCH! NCHUCS MATCH 2 -bit smoother 26

Cluster-Based Scan Chain Reorder o o o Layout surface divided into clusters Reorder limited in single cluster Snake-like global routing Multiple scan chains Single scan chain NCHUCS 27

Example o Routing s 15850 n 611 scan cells 1 cluster 256 clusters NCHUCS Silicon Ensemble 28

Optimal Cluster Size o o Is there an optimal cluster size? Observation n n o Large clusters--long vertical connection Small clusters--more horizontal crossings How to find optimal cluster size n n Find an expression of total wirelength Take its derivative with respect to cluster size c NCHUCS 29

Estimate Wirelength in a Cluster (1) o Two types of order n Random order CL 2 CL 1 sc 4 sc 1 sc 5 sc 2 sc 3 n Sorted according to x-cooridnate CL 1 sc 2 sc 3 NCHUCS 30

Estimate Wirelength in a Cluster (2) o How to estimate the distance between two cells n n n Manhattan distance Horizontal and vertical distances are independent Assuming cells are randomly distributed w sc 1(X 1, Y 1) h sc 2(X 2, Y 2) (0, 0) NCHUCS 31

Estimate Wirelength in a Cluster (3) o o Expected vertical distance between two cells Expected horizontal distance between two cells n n Random order: w/3 Sorted order o Summation of all horizontal distances: w NCHUCS 32

Estimate Wirelength in a Cluster (4) o Random order n o N: # cells, c 2: #clusters Sorted order NCHUCS 33

Optimal Number of Clusters (1) o Random order n o Assuming H W, N/c 2 1 Sorted order n Assuming H W, N/c 2 3 NCHUCS 34

Optimal Number of Clusters (2) o Reordering algorithm n n n o Larger clusters give better results Almost no reordering when N/c 2 1 Choose sorted order if no special order is preferred Optimal cluster size 2 N/c 2 3 NCHUCS 35

Outline o o o ■ o Overview Scan chain order: does it matter? Cluster-based reordering for lowpower BIST Experimental results Future work NCHUCS 36

Experimental Results—Wire Length (1) o 2 -bit smoother NCHUCS 37

Experimental Results—Wire Length (2) o 3 -bit smoother NCHUCS 38

Experimental Results—Fault Coverage (1) o 2 -bit smoother NCHUCS 39

Experimental Results—Fault Coverage (2) o 3 -bit smoother NCHUCS 40

Optimal Number of Cells per Cluster Circuit WL (mm) -- SE #cluster S 641 2. 71 36 S 713 2. 67 S 953 #cells/cluster 2 -bit smoother 3 -bit smoother GS WL (mm) Red (%) 1. 50 2 2. 83 -4. 24 3 2. 84 -4. 58 36 1. 50 4 2. 90 -7. 93 10 2. 90 -7. 93 3. 30 16 2. 81 3 3. 68 -10. 33 9 3. 69 -10. 57 S 1196 4. 74 16 2. 00 2 5. 08 -6. 69 7 5. 09 -6. 88 S 1423 5. 70 36 2. 53 1 6. 04 -5. 53 3 6. 04 -5. 63 S 5378 14. 57 100 2. 14 4 15. 78 -7. 67 4 15. 77 -7. 61 S 9234 22. 68 100 2. 47 1 23. 21 -2. 28 8 23. 75 -4. 51 S 13207 45. 22 256 2. 73 3 44. 74 1. 06 6 45. 49 -0. 59 S 15850 53. 40 256 2. 39 10 51. 97 2. 68 2 50. 98 4. 53 S 38417 136. 94 576 2. 89 1 123. 3 9. 96 6 125. 72 8. 19 S 38584 187. 89 576 2. 54 10 177. 82 5. 36 7 178. 14 5. 19 SE: Silicon Ensemble NCHUCS 41

Test Efficienct Circu TL i t Test Efficiency (%) Mar k o v LF 2 -bit smoother S R SE Sou r c e 3 -bit smoother Optimal SE Clus ter Optimal Clus ter BIS T S 923 4 728 98. 95. 93. 4 5 0 4 8 2 2 6 S 132 406 97. 98. 92. 0 7 8 9 7 7 7 8 0 3 S 158 377 98. 96. 93. 5 6 3 4 4 0 7 1 1 7 83. 95. 47 3 9 92. 00 6 4 87. 72 83. 97. 84 90. 97. 69 NCHUCS 6 92. 79 2 42

Comparison of Average Power Circuit #scan cells TL FC (%) LFSR 2 -bit smoother* 3 -bit smoother* LT-RTPG (k=3) FC (%) SE Opt. cluster AP Red (%) FC (%) AP Red (%) S 641 54 4096 97. 42 94. 19 95. 91 57. 41 87. 31 90. 75 85. 65 89. 64 36. 9 S 713 54 4096 91. 94 87. 99 89. 88 58. 15 83. 70 86. 36 93. 34 37. 8 S 953 45 8192 98. 99 86. 41 97. 97 55. 47 54. 26 80. 17 84. 95 85. 61 58. 7 S 1196 32 4096 95. 49 82. 63 92. 71 56. 58 59. 40 78. 72 85. 40 95. 87 30. 2 S 1423 91 4096 97. 89 95. 40 98. 59 57. 25 88. 75 96. 29 85. 09 97. 08 49. 7 S 5378 214 65536 98. 96 97. 91 98. 56 58. 51 90. 26 95. 50 84. 75 97. 08 44. 0 S 9234 247 131072 89. 67 87. 91 91. 40 59. 37 77. 49 86. 78 85. 53 91. 63 55. 7 S 13207 700 40677 97. 42 91. 25 96. 37 62. 67 82. 17 86. 24 87. 39 - - S 15850 611 37767 93. 06 90. 12 94. 43 58. 21 87. 27 89. 44 84. 96 - - S 38417 1664 81984 96. 67 94. 26 95. 42 60. 73 92. 97 93. 93 84. 93 - - S 38584 1464 82055 95. 70 91. 05 95. 00 60. 87 86. 14 91. 58 84. 81 - - - 95. 75 90. 83 95. 11 58. 66 80. 88 88. 46 85. 44 92. 89 44. 71 Average *Full scan; : only state vectors are scanned NCHUCS 43

Peak Power o o Capture-cycle power is not reduced Still provide some improvement Circuit PP Red (%) 2 -bit smoother 3 -bit smoother S 5378 13. 31 11. 64 S 9234 13. 75 16. 68 S 13207 12. 65 19. 96 S 15850 13. 60 20. 23 S 38417 13. 78 19. 24 S 38584 13. 12 18. 01 Average 13. 37 17. 63 NCHUCS 44

Outline o o ■ Overview Scan chain order: does it matter? Cluster-based reordering for lowpower BIST Experimental results Future work NCHUCS 45

Conclusion o Scan chain reorder is very effect to deal with n n n o Test power Scan-based delay test Fault coverage in BIST Need to consider n Physical design infromation NCHUCS 46

Future Work o o Fast reordering algorithm for delay test Integrate reordering algorithm, considering n n Test power Delay test coverage Wire length Other issues NCHUCS 47

THE END Thank You! NCHUCS 48