SATBased Optimization with DontCares Revisited Alan Mishchenko Robert

SAT-Based Optimization with Don’t-Cares Revisited Alan Mishchenko Robert Brayton Department of EECS UC Berkeley

Overview l l Motivation for revisiting don’t-cares Overview of proposed improvements in l l l Target node selection Windowing and candidate divisor selection Target node support minimization Deriving updated circuit structure Experiments Conclusion 2

Motivation l Don’t-cares are often not used because l l Methods are hard to follow and not general enough Computation is believed to be slow / unscalable Improvements are not significant In this work, we address these limitations l l l Clarify and unify the use of don’t-cares Show to use them efficiently and scalably Demonstrate a substantial improvement in Qo. R

A Don’t-Care-Based Opt. Flow Input netlist Iterator over nodes to be optimized Output netlist Candidate divisor selection and windowing Node support minimization Node selection / ordering depends on opt. criteria (area, delay, power, etc) If a transform is accepted, update the network, resource limits, and node selection criteria Synthesis of updated logic structure

Improved Target Node Selection l In the past, we considered all nodes in a topological order l Now, selection depend on the optimization goal In delay optimization, we maintain a priority queue for delay-critical nodes, in which they are sorted by the number of critical PI-to-PO paths going through them l l l In area optimization, we maintain a priority queue for delay -critical nodes, in which they are sorted by the size of their MFFC l l Each time, we target the node that can reduce delay the most Each time, we target the node that can reduce area the most In both cases, we choose nodes to maximize the gains

Improved Divisor Selection l In the past, we did windowing before divisor selection l Now, we do divisor selection before windowing l l l If we start with windowing, we may end up including logic that is not needed for achieving the optimization goal For example, if the goal of optimization is to reduce delay at a node, we should find useful candidate divisors first, and then compute a window for them, not vice versa Divisor selection depends on the optimization goal l For example, to reduce delay at a node, we consider divisors in the TFI of the critical fanins; other candidate divisors are not useful and can be skipped to save runtime

Improved Windowing l In the past, window scope was fixed in advance l Now, windowing divisor-dependent l l Windowing is reconvergence-driven l l l That is, we construct a window for a given set of divisors Only that part of the TFO of the target node is included in the window, which has reconvergence with the included part of the TFI For example, if a part of the TFI or the TFO is disjoint-support with the rest of the window, we replace it by a free variable; this reduces window size and runtime without losing any optimization capabilities, because disjoint-support logic cones to do generate additional don’t-cares Windowing takes into account “observability leaks” l l For example, if one of the fanouts of the target node is a PO, there is no need to consider observability don’t-cares even if the TFO has reconvergence with the TFI, because the node’s function cannot change The same principle holds in a more general sense: Anytime fanout f of node m in the TFO of the target node n has no recovergence with the TFI, the window boundary stops at node m (there is no need to include fanouts of node m into the window of node n)

Improved Support Minimization l In the past ( “mfs” and “mfs 2”), used a heuristic procedure, which tries to remove some old fanins and add new fanins, in such as way that (1) optimization goal is achieved, (2) the support is feasible, (3) the support is minimized l Now use a new procedure (sat_minimize_assumptions), which takes a priority-ordered list of all candidate divisors, and selects a minimal feasible subset of them, which satisfies the following criterion: a candidate divisor is included in the subset if and only if there is no other node with lower priority that can do the job

New Procedure: sat_minimize_assumptions() l l The procedure takes a set of assumptions, which makes the given problem instance UNSAT It returns a minimized set, for which the problem is UNSAT, while only including the necessary assumptions in the priority order int sat_minimize_assumptions( sat_solver* s, int * p. Lits, int n. Lits ) { if only one assumption is left, check if the problem is UNSAT, return 0; otherwise, return 1 divide assumptions into two parts (left and right) assume the left part solve recursively for the right part swap the parts solve recursively for the left part union solutions }

Improved Logic Structure Synthesis l In the past, one node at a time is targeted and changed, by adding/removing fanins l Now, we use QBF to synthesize a LUT structure meeting the optimization goal at each target node l QBF can handle multi-output targets QBF can produce multi-node LUT structures QBF is fast in this application because l l l Relatively small LUT structures are considered Connectivity is limited due to delay profile Don’t-cares leads to fewer care minterms to satisfy

Conclusion l This work proposes new heuristics and improved algorithms for using don’t-cares l For the first time, in our work on don’t-cares: l l SAT-based optimization is used for delay optimization Goal-oriented target-node selection is used Multi-node LUT structures are synthesized Multi-output targets can be used

Abstract l The paper describes a SAT-based framework for logic optimization with don’t-cares aimed at reducing delay and area after LUT mapping. While individual components of the framework are known, its novelty is in synergistically combining the following aspects of SATbased optimization for the first time: a) improved computation of delay and area criticality, b) novel reconvergence-driven windowing and divisor selection, c) the use of complete don’t-cares, and d) SAT-based generation of new useful cut-points in the network. Experimental results show that a preliminary implementation improves delay after LUT mapping at the cost of some area increase, compared to previous methods.