SAR ADC Tao Chen Successiveapproximation Register SAR ADC

SAR ADC Tao Chen

Successive-approximation Register (SAR) ADC Chapter 17 Figure 05 Read chapter 17. 2 2

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Example timing diagram • At “convert start”, SHA grabs a sample and hold its value • Set DAC MSB to 1 as test bit, rest bits set to 0, • DAC output compared to sample held • If comparator output = 1, keep test bit as 1, else set test bit = 0 • If test bit is LSB, reset “busy” and signal end of conversion • Else, move test bit to next lower bit, and set it to 1, generate DAC output • At end of conversion, DAC input code sent out as ADC output code 4

Charge redistribution implementation

Sampling Phase Vin = 1. 3 Vref = 5 V

Conversion Phase 0 Vin = 1. 3 V Vref = 5 V

Conversion Phase 1 Vin = 1. 3 Vref = 5 V 0

Conversion Phase 2 Vin = 1. 3 Vref = 5 V 1

Conversion Phase 3 Vin = 1. 3 Vref = 5 V 0

• For N-bit ADC • Conversion Phase 0 can be skipped • Non-overlapping Clock

Chapter 17 Figure 10

Segmented CDAC 14

Hybrid ADC

Hybrid ADC

Design Consideration • Comparator: high speed, high resolution • Capacitor: matching & KT/C (area) • Switch: sampling time & conversion time

Project R-string R 2 R Flash SAR Size R R-string CDAC (size C) Segmentation Decoder Comparator Switch Encoder SAR Logic Buffer Bubble rm Switch Clock/Timing State-of-the-art ADCs http: //web. stanford. edu/~murmann/adcsurvey. html Power ENOB Speed Area

Simulation • Data converter simulation is very slow! • Histogram test, spectral test takes hours to days! • Server load is high at the end of the semester! • Server crashes very often !! • Start your project earlier !!!