Sampa testing 13 08 14 Arild Velure FPGA

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Sampa testing 13. 08. 14 Arild Velure

Sampa testing 13. 08. 14 Arild Velure

FPGA testboard design MUX Command Control Module HPS Uart to bus Memory Clock Manager

FPGA testboard design MUX Command Control Module HPS Uart to bus Memory Clock Manager Data manager HSMC So. C-Kit Board • Communication / Interface – UART to bus • • – – Software/ DAQ § Link to SAMPA carrier board Data is transported to memory through a DMA Ethernet • • Gives direct access to internal bus from uart Switching between Linux terminal and bus is done online with a switch HSMC • • SAMPA Kernel module in Linux takes data from memory and transmits it to DAQ § Functional testing § Onboard SAMPA emulator in C § Labview reused from ALTRO test (backup plan) DAQ and data analysis § Root program for DAQ § Date program (for MPW 2)

Status of design • FPGA design – Design 85% done • Kernel module and

Status of design • FPGA design – Design 85% done • Kernel module and some parts of the data manager is not finished • All other modules tested and working – Ethernet interface tested to 670 Mbits/s • Further optimizations might be possible • DAQ/Root – Can receive, store and display data from Ethernet – Can communicate with Sampa/testboard through UART – Working on configuration interface and multi-channel support • Functional test program – SAMPA emulator • Need to update ALTRO++ code (ALTRO emulator) for latest changes – Labview • Filter models need to be updated from ALTRO implementation • Testboard interface needs to be implemented – Is already modular so should not be too difficult

Plans (I) • Functional verification DSP – By tapping the signal path at various

Plans (I) • Functional verification DSP – By tapping the signal path at various stages of the DSP filters, the filters can be verified against a high -level model in the testprogram – By supplying the Sampa with a test signal from the testboard a bitwise comparison of the input data vs output data can be run continuously

Plans (II) • GEM prototype testing – Prototype in development – Provided by Wigner.

Plans (II) • GEM prototype testing – Prototype in development – Provided by Wigner. RCP Group of Hungary – Signal to noise test : Verify with GEM detector at which effective GEM the signal to noise value for MIPs would be 20: 1 for the small pads (IROC) and >=30: 1 for the medium and large pads (OROC).

Plans (III) • GEM prototype testing – Noise tests on GEM detector with and

Plans (III) • GEM prototype testing – Noise tests on GEM detector with and without input protection (resistors and diodes) – Input protection testing • Equip all pads of a 10 x 10 cm 2 detector with readout, inject a radioactive gas into the detector, increase the HV to have regular sparks, and hopefully see that no SAMPAs break. Then we remove input protection and probably see that sometimes channels break. • Planned for MPW 2

Plans (IIII) • Irradiation tests – Single Event Effects • High Energy Hadrons (HEH)

Plans (IIII) • Irradiation tests – Single Event Effects • High Energy Hadrons (HEH) may lead to – Single Event Upset (SEU) – Single Event Latch-up (SELs) • Estimated Flux (HEH) ~3. 4 k. Hz/cm^2 • Tested with shift register and possibly pedestal memory • Testing at external high energy facility – Total Ionizing Dose • Inner most partitions ~ 2 k. Rad • Tested through monitoring of power consumption and operation • Can be tested at local facilities (Oslo/Brazil)