SAJE Silicon Aid JTAG Environment Overview Very Short

SAJE Silicon. Aid JTAG Environment Overview – Very Short Silicon. Aid Solutions, Inc. Confidential

SAJE JTAG Product Summary Synthesis Verification Debugger JTS JTV JTD Generate P 1687 JTAG Designs Verify BSDL and JTAG Design Provide JTAG Debug environment Silicon. Aid Solutions, Inc. Confidential

P 1687 Activities • • • YES – P 1687 Exists and works Si. Aid is making significant investment Alpha software demos available Beta Software in development Partnering with key companies Silicon. Aid Solutions, Inc. Confidential

P 1687 Simplified Basic Flow Wrap IP P 1687 Synthesis Wrap Existing IPs with 1500 wrapper and enhance for P 1687 Automatically integrate wrapped IP, insert JTAG with P 1687 compliant structures Pattern Conversion Convert Wrapped IP vectors into Chip Generate Testbench Verify JTAG and generate testbench to Simulate Silicon. Aid Solutions, Inc. Confidential level JTAG patterns sim all test including IP patterns

The BIG PICTURE Insert JTAG and 1687 Logic JTS Generate Simulation and Chip Vectors Exhaustive semantic and compliance JTV checking Simulate CHIP (JTD) Verify JTAG and generate Leverages Design data testbench to sim all test to drive and debug including IP patterns JTAG hardware Silicon. Aid Solutions, Inc. Confidential Subset of Patterns for Board level support (SVF) BOARD Matches Vectors by Vector: Simulation, CHIP, and BOARD

Board SVF Debug Flow Board Test Fails Generate Patterns Debugger Silicon. Aid Solutions, Inc. Confidential Verify JTAG and generate testbench to sim all test including IP patterns Simulate

JTV - Typical ATE Flow Company A BSDL J T V • No Verilog Netlist • No Simulation Your Specific Guidelines Silicon. Aid Solutions, Inc. Confidential STIL Vector file

1687 Network GUI Serial ATPG Silicon. Aid Solutions, Inc. Confidential

1687 Board SVF Debug Flow Board Test Fails 1687 ATPG Board or ATE Debugger Silicon. Aid Solutions, Inc. Confidential Understands 1687 network and BSDL, Generates selected tests, SVF output Interactive debugger – leverages design info into ATE and Board tests

Silicon. Aid Solutions JTAG DEBUGGER TOOL (JTD) Silicon. Aid Solutions, Inc. Confidential

WHY JTD • New Product Introduction/Evaluation • Proto-typing pre-Silicon on Xilinx Boards • Works in concert with ATE testers • Debug capabilities to identify internal registers failing on TDO • Tracks JTAG state machine on vector per vector basis • Fast, easy, quick way to drive and observe standard JTAG signals • Leverages JTV output to enhance debugging capability Silicon. Aid Solutions, Inc. Confidential

JTD Major Features • Hardware Interface using USB 2. 0 • JTAG 5 pin connector • Can drive evaluation board, Apps board, burn in board, ATE tester board, and more…. . • Compares expected values for TD 0 • Supports run till FAIL, STEP, etc. . • Leverages patterns from JTV • Supports external SVF patterns Silicon. Aid Solutions, Inc. Confidential

Initial JTD Window Debugger run JTAG State and controls Machine Viewer Online Help and patterns Displays Fails Displays expected apps notes on actual register and actual data in waveforms Silicon. Aid Solutions, Inc. Confidential

Debugger Window Flow Control Header Info Fails Results Window log Window Silicon. Aid Solutions, Inc. Confidential Command line

Register Viewer Failing bits are graphically displayed and bit descriptions pop up when clicked. Black – Expect 1 White – Expect 0 Red - Failed Silicon. Aid Solutions, Inc. Confidential

Waveform Viewer Capturing internal registers not accessible via pins on the device. Silicon. Aid Solutions, Inc. Confidential

JTAG State Machine Status is graphically displayed real time as the vectors are steps in the debugger window Silicon. Aid Solutions, Inc. Confidential

DEMO JTD USB 2. 0 JTAG Signals TMS TDI TDO TCK TRST Silicon. Aid Solutions, Inc. Confidential Apps Board

What is JTV ? Silicon. Aid Solutions, Inc. Confidential

Silicon. Aid Solutions JTAG VERIFICATION TOOL (JTV) Silicon. Aid Solutions, Inc. Confidential

JTV - Purpose • Verification support for JTAG providers – Focus is chip-level verification • Provide an efficient means to – – Insure correct JTAG functionality on first-pass silicon Deliver a verified BSDL file for customer usage Deliver high quality production test vectors Diagnose fab-related pad or JTAG logic yield problems • Goal is to – Eliminate customer BSDL and/or JTAG-related problems Silicon. Aid Solutions, Inc. Confidential

JTV Design Flow Diagram Silicon. Aid Solutions, Inc. Confidential

SAJE JTV simplified Flow JTAG Generation BSDL • Legacy Designs • Any 3 rd Party tool • Internally developed SAJE JTV • Independent verification that BSDL matches your Design • Verifies Design is IEEE 1149. 1 & 1149. 6 compliant • Generates full suite of Production test vectors • Generates verilog testbench & tests for verification • Proven technology on hundreds of production designs • More than 12 years + of success Production Ready Patterns User selectable test Testbench Netlist with JTAG Any 3 rd Party Simulator Silicon. Aid Solutions, Inc. Confidential

Board Companies Specific Benefits • • • Screen for incoming BSDL Chip level ATE pattern Board Level targeted patterns for a chip No Verilog required Standardized test bench for all incoming design (if chip provider supplies verilog) Silicon. Aid Solutions, Inc. Confidential

Incoming BSDL and Verilog Process Flow Company A Company B Company C J T V Company X Checker Company D Company X Specific Guidelines Silicon. Aid Solutions, Inc. Confidential Release to Production

JTV - Typical ATE Flow Company A BSDL J T V • No Verilog Netlist • No Simulation Company X Specific Guidelines Silicon. Aid Solutions, Inc. Confidential STIL Vector file

Summary • Simulation, ATE, and Board can have same patterns applied – Helps solve the NPF problems! • Alpha 1687 Flow available • JTD - Debugger works at chip level and plans to support board level in the future • JTV is a mature product with 15+ years of continual history and usage • 1149. 1 and 1149. 6 Chip verification and compliance checking • Verifies BSDL matches design • SVF Patterns will soon be portable to board test • Tools be used in a custom or JTAG synthesis design flow • Leverages Design data in ATE and Board Debug Silicon. Aid Solutions, Inc. Confidential

Jim Johnson : President email: jim. johnson@siliconaid. com phone: (512) 694 -4261 Silicon. Aid Solutions, Inc. Confidential

Silicon. Aid Solutions, Inc. Confidential