RS232 Port Discussion D 10 1 RS232 voltage

RS-232 Port Discussion D 10. 1

RS-232 voltage levels: +5. 5 V (logic 0) -5. 5 V (logic 1) Loop feedback

PC: DTE female connector Spartan-3 board: DCE male connector Straight-through cable

Note: Tx. D (pin 2) on Spartan-3 DCE connector is connected to RD (pin 2) on the PC DTE connector

UART clock frequency = 16 x Baud rate or 64 x Baud rate

Standard ASCII Codes Table 9. 2 Standard ASCII codes Dec 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Hex 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 16 32 48 64 80 96 112 0 1 2 3 4 5 6 7 NUL SOH STX EOT ENQ ACK BEL BS HT LF VT FF CR SO SI DLE DC 1 DC 2 DC 3 DC 4 NAK SYN ETB CAN EM SUB ESC FS GS RS US blank 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ ] ^ _ ! " # $ % & ' ( ) * + , . / a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~ DEL

How would you make the following hardware Tx UART? 8 -bit parallel data comes in tx_data(7: 0) and is loaded into a transmit buffer txbuff when tdre is high. When ready goes high the contents of txbuff is sent out Tx. D as asynchronous serial data. When txbuff is empty, tdre is set to 1.

UART Transmit State Diagram

VHDL Canonical Sequential Network s(t+1) next state State Register x(t) present input Combinational Network init process(clk, init) clk process(present_state, x) s(t) present state present z(t) output

VHDL Mealy Machine process(present_state, x) s(t+1) C 1 x(t) present input next state State Register init s(t) present state process(present_state, x) clk process(clk, init) z(t) C 2

VHDL Moore Machine s(t+1) C 1 next state x(t) present input process(present_state, x) State Register init z(t) s(t) present state C 2 process(present_state) clk process(clk, init)

VHDL Canonical Sequential Network s(t+1) next state Combine into a single process(present_state, x) State Register x(t) present input Combinational Network init s(t) present state process(clk, init) clk present z(t) output

UART Transmit State Diagram

entity uart_tx is port( clk : in STD_LOGIC; clr : in STD_LOGIC; tx_data : in STD_LOGIC_VECTOR(7 downto 0); ready : in STD_LOGIC; tdre : out STD_LOGIC; Tx. D : out STD_LOGIC ); end uart_tx;

architecture uart_tx of uart_tx is type state_type is (mark, start, delay, shift, stop); signal state: state_type; signal txbuff: STD_LOGIC_VECTOR (7 downto 0); signal baud_count: STD_LOGIC_VECTOR (11 downto 0); signal bit_count: STD_LOGIC_VECTOR (3 downto 0); constant bit_time: STD_LOGIC_VECTOR (11 downto 0) : = X"A 28"; begin 9600 baud

uart 2: process(clk, clr, ready) begin if clr = '1' then state <= mark; txbuff <= "0000"; baud_count <= X"000"; bit_count <= "0000"; Tx. D <= '1'; elsif (clk'event and clk = '1') then case state is when mark => -- wait for ready bit_count <= "0000"; tdre <= '1'; if ready = '0' then state <= mark; txbuff <= tx_data; else baud_count <= X"000"; state <= start; -go to start end if;

when start => -- output start bit baud_count <= X"000"; Tx. D <= '0'; tdre <= '0'; state <= delay; -go to delay when delay => -- wait bit time tdre <= '0'; if baud_count >= bit_time then baud_count <= X"000"; if bit_count < 8 then -- if not done state <= shift; -go to shift else -- else state <= stop; -go to stop end if; else baud_count <= baud_count + 1; state <= delay; -stay in delay end if;

when shift => -- get next bit tdre <= '0'; Tx. D <= txbuff(0); txbuff(6 downto 0) <= txbuff(7 downto 1); bit_count <= bit_count + 1; state <= delay; when stop => -- stop bit tdre <='0'; Tx. D <= '1'; if baud_count >= bit_time then baud_count <= X"000"; state <= mark; else baud_count <= baud_count + 1; state <= stop; end if; end case; end if; end process uart 2; end uart_tx;

Test Transmit UART Set slide switches to some ASCII code and then press button 0 to send ASCII code out serial port. SW BTN(0)

entity tx_tst_ctrl is port( clk : in STD_LOGIC; clr : in STD_LOGIC; btn : in STD_LOGIC; tdre : in STD_LOGIC; ready : out STD_LOGIC ); end tx_tst_ctrl;

architecture tx_tst_ctrl of tx_tst_ctrl is type state_type is (wtbtndn, wttdre, load, wtbtnup); signal state: state_type; begin ctrl: process(clk, clr, btn, tdre) begin if clr = '1' then state <= wtbtndn; ready <= '0'; elsif (clk'event and clk = '1') case state is when wtbtndn => -if btn = '0' then -state <= wtbtndn; -ready <= '0'; else ready <= '0'; state <= wttdre; -end if; then wait for btn if bnt up stay in wtbtndo else go to wttdre

when wttdre => if tdre = '0' then state <= wttdre; ready <= '0'; else state <= load; ready <= '0'; end if; when load => ready <= '1'; state <= wtbtnup; -- wait for tdre = 1 -- if tdre = 0 -stay in wtdone -- else go to load -- output ready -- go to wtbtnup

when wtbtnup => if btn = '1' then state <= wtbtnup; ready <= '0'; else ready <= '0'; state <= wtbtndn; end if; end case; end if; end process ctrl; end tx_tst_ctrl; -- wait for btn up -- if btn down -stay in wtbtnup -- else go to wtbtndn

Test Transmit UART Top-level design entity uart_tx_test is port ( mclk : in STD_LOGIC; SW : in STD_LOGIC_VECTOR(7 downto 0); BTN : in STD_LOGIC_VECTOR(3 downto 0); LD : out STD_LOGIC_VECTOR(7 downto 0); Tx. D : out STD_LOGIC ); end uart_tx_test; Pin "R 13"

architecture uart_tx_test_arch of uart_tx_test is component uart_tx port( clk : in STD_LOGIC; clr : in STD_LOGIC; tx_data : in STD_LOGIC_VECTOR(7 downto 0); ready : in STD_LOGIC; tdre : out STD_LOGIC; Tx. D : out STD_LOGIC ); end component; component tx_tst_ctrl port( clk : in STD_LOGIC; clr : in STD_LOGIC; btn : in STD_LOGIC; tdre : in STD_LOGIC; ready : out STD_LOGIC ); end component;

component debounce is port ( inp, clk, clr: in std_logic; outp: out std_logic ); end component; signal clr, clk, cclk: std_logic; signal tdre, ready, BTN 0: std_logic; signal clkdiv : std_logic_vector(23 downto 0); begin

-- Divide the master clock (50 Mhz) down to a lower frequency. process (mclk) begin if clr = '1' then clkdiv <= "000000000000"; elsif mclk = '1' and mclk'Event then clkdiv <= clkdiv + 1; end if; end process; clk <= clkdiv(0); -- 25 MHz cclk <= clkdiv(17); -- 190 Hz LD(7) LD(6) LD(5) LD(4) LD(3) LD(2) LD(1) LD(0) <= <= BTN(1); BTN(2); BTN(1); tdre; clr <= BTN(3);

U 1: uart_tx port map (Tx. D => Tx. D, clk => clk, clr => clr, ready => ready, tx_data => SW, tdre => tdre); U 2: tx_tst_ctrl port map (clk => clk, clr => clr, btn => BTN 0, tdre => tdre, ready => ready); U 3: debounce port map (inp => BTN(0), clr => clr, clk => cclk, outp => BTN 0); end uart_tx_test_arch; BTN(0) SW

How would you make the following hardware Rx UART? 8 -bit asynchronous serial data comes in Rx. D and fills up the shift register data_rx. When data_rx is full, rdrf is set to 1. rdrf is cleared to zero by bringing clrflg high. The framing error flag FE is set to 1 if the stop bit is not 1.

UART Receive State Diagram

entity uart_rx is port( Rx. D : in STD_LOGIC; clk : in STD_LOGIC; clr : in STD_LOGIC; rdrf_clr : in STD_LOGIC; rdrf : out STD_LOGIC; FE : out STD_LOGIC; rx_data : out STD_LOGIC_VECTOR(7 downto 0) ); end uart_rx;

architecture uart_rx of uart_rx is type state_type is (mark, start, delay, shift, stop); signal state: state_type; signal rxbuff: STD_LOGIC_VECTOR (7 downto 0); signal baud_count: STD_LOGIC_VECTOR (11 downto 0); signal bit_count: STD_LOGIC_VECTOR (3 downto 0); signal rdrf_set, fe_set, cclr 8, rxload: STD_LOGIC; constant bit_time: STD_LOGIC_VECTOR (11 downto 0) : = X"A 28"; constant half_bit_time: STD_LOGIC_VECTOR (11 downto 0) : = X"514"; begin 9600 baud

uart 2: process(clk, clr, rdrf_clr) begin if clr = '1' then state <= mark; rxbuff <= "0000"; baud_count <= X"000"; bit_count <= "0000"; FE <= '0'; elsif rdrf_clr = '1' then rdrf <= '0'; elsif (clk'event and clk = '1') then case state is when mark => -- wait for start bit baud_count <= X"000"; bit_count <= "0000"; if Rx. D = '1' then state <= mark; else FE <= '0'; state <= start; -go to start end if;

when start => if baud_count >= half_bit_time baud_count <= X"000"; state <= delay; else baud_count <= baud_count + state <= start; end if; when delay => if baud_count >= bit_time then baud_count <= X"000"; if bit_count < 8 then state <= shift; else state <= stop; end if; else baud_count <= baud_count + state <= delay; end if; -- check for start bit then 1;

when shift => -- get next bit rxbuff(7) <= Rx. D; rxbuff(6 downto 0) <= rxbuff(7 downto 1); bit_count <= bit_count + 1; state <= delay; when stop => rdrf <= '1'; if Rx. D = '0' then FE <= '1'; else FE <= '0'; end if; state <= mark; end case; end if; end process uart 2; rx_data <= rxbuff; end uart_rx;

Test of UART

Test Receive UART Receive ASCII code sent from terminal program on PC when key is pressed and display on LEDs.

Test Transmit UART Echo back ASCII code sent from PC. rdrf_clr

entity test 2_rx_ctrl is port( clk : in STD_LOGIC; clr : in STD_LOGIC; rdrf_clr : out STD_LOGIC ); end test 2_rx_ctrl; architecture test 2_rx_ctrl of test 2_rx_ctrl is type state_type is (wtrdrf, load); signal state: state_type;

begin ctrl: process(clk, clr, rdrf) begin if clr = '1' then state <= wtrdrf; rdrf_clr <= '0'; elsif (clk'event and clk = '1') then case state is when wtrdrf => rdrf_clr <= '0'; if rdrf = '0' then state <= wtrdrf; else state <= load; end if; when load => rdrf_clr <= '1'; state <= wtrdrf; end case; end if; end process ctrl; end test 2_rx_ctrl;

entity uart_test 2 is Top-level test of UART port ( mclk : in STD_LOGIC; BTN 3 : in STD_LOGIC; Rx. D : in STD_LOGIC; LD : out STD_LOGIC_VECTOR(7 downto 0); Tx. D : out STD_LOGIC ); end uart_test 2; architecture uart_test 2_arch of uart_test 2 is component uart_tx port( clk : in STD_LOGIC; clr : in STD_LOGIC; tx_data : in STD_LOGIC_VECTOR(7 downto 0); ready : in STD_LOGIC; tdre : out STD_LOGIC; Tx. D : out STD_LOGIC ); end component;

component tx_tst_ctrl port( clk : in STD_LOGIC; clr : in STD_LOGIC; btn : in STD_LOGIC; tdre : in STD_LOGIC; ready : out STD_LOGIC ); end component; component uart_rx port( Rx. D : in STD_LOGIC; clk : in STD_LOGIC; clr : in STD_LOGIC; rdrf_clr : in STD_LOGIC; rdrf : out STD_LOGIC; FE : out STD_LOGIC; rx_data : out STD_LOGIC_VECTOR(7 downto 0) ); end component;

component test 2_rx_ctrl port( clk : in STD_LOGIC; clr : in STD_LOGIC; rdrf_clr : out STD_LOGIC ); end component; signal clr, clk, cclk: std_logic; tdre, rdrf_clr, FE, ready, btn: std_logic; clkdiv : std_logic_vector(23 downto 0); data : std_logic_vector(7 downto 0);

begin -- Divide the master clock (50 Mhz) down to a lower frequency. process (mclk) begin if clr = '1' then clkdiv <= "000000000000"; elsif mclk = '1' and mclk'Event then clkdiv <= clkdiv + 1; end if; end process; clk <= clkdiv(0); -- 25 MHz cclk <= clkdiv(17); -- 190 Hz LD <= data; clr <= BTN 3; btn <= rdrf_clr;

U 1: uart_tx port map (Tx. D => Tx. D, clk => clk, clr => clr, ready => ready, tx_data => data, tdre => tdre); U 2: uart_rx port map (Rx. D => Rx. D, clk => clk, clr => clr, rdrf_clr => rdrf_clr, rx_data => data, rdrf => rdrf, FE => FE); U 3: tx_tst_ctrl port map (clk => clk, clr => clr, tdre => tdre, btn => btn, ready => ready); U 4: test 2_rx_ctrl port map (clk => clk, clr => clr, rdrf => rdrf, rdrf_clr => rdrf_clr); end uart_test 2_arch;