RMU Status INFN Roma Tre Group Stefano Mari

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RMU Status INFN Roma Tre Group Stefano Mari, Andrea Fabbri, Paolo Branchini, Domenico Riondino,

RMU Status INFN Roma Tre Group Stefano Mari, Andrea Fabbri, Paolo Branchini, Domenico Riondino, Cristina Martellini

CD trigger block schematic 1/11

CD trigger block schematic 1/11

RMU Reorganize & Multiplexing Unit supply Supply, slow control RMU board 100 pin connector

RMU Reorganize & Multiplexing Unit supply Supply, slow control RMU board 100 pin connector Scheda K 7 100 pin onnector supply slow control ethernet link Supply, slow control WR Node Specification: 125 input link from BEC organized in 7 RM Unit: 18 x 1 Gb/s input link each 3 x 6. 25 Gb/s output link each Scheda K 7 100 pin connector Each RMU has 3 separate FPGA board with 7 x input link and 1 x output link supply Supply, slow control Fanout can be improved with passive 2 x or 4 x splitter. Dedicated test can be performed. 100 pin connector Scheda K 7 Splitters with calibrated propagation delay will be needed to ensure isosynchronous transmission. 100 pin connector 2/11

RMU status 3/11

RMU status 3/11

RMU status Mother Board v 1. 0 Fit commercial 2 U case for 19’’

RMU status Mother Board v 1. 0 Fit commercial 2 U case for 19’’ racks. Supplies and control signals routing between different boards. I 2 C bus allows USOP slow control of the system V 1. 0 is equipped with clock fan-out from USOP to allow clock distribution test. Mother Board v 2. 0 version was tested during summer. It works fine, but a different connector position is preferable for WR board. V 2. 1 (final version) will be during November 4/11

RMU status Power Board v 1. 0 Four DCDC modules for FPGA supplies. Each

RMU status Power Board v 1. 0 Four DCDC modules for FPGA supplies. Each one is followed by a power monitor (I/V measurement). Preliminary test is ongoing. Minor issue with capacitor footprint will be corrected before production. 1. 8 V +5 V In 1. 0 V 3. 3 V 1. 2 V Control signals Output Voltages Power board block schematics 5/11

RMU status USOP v 2. 0 Developed by INFN Roma Tre and INFN Napoli

RMU status USOP v 2. 0 Developed by INFN Roma Tre and INFN Napoli for Belle II experiment. Ten boards on-line at KEKB since 2016 without any failures. Redundant ethernet link for remote control/diagnostic. Development of FW for RMU slow control is ongoing: • Power supply monitor • Transciever monitor • Temperature monitor 6/11

RMU status K 7 Board v 1. 0 Debug phase completed: - FPGA ok

RMU status K 7 Board v 1. 0 Debug phase completed: - FPGA ok - Measured BER (with Xilinx IBERT) on each link is less than 10 -15 @ 8 Gbit/s (no bit error when 1015 is trasmitted) - Negligible cross-talk FW development for isosyncrhonous is ongoing K 7 Board v 2. 0 PCB of v 2. 0 board is under characterizatio. - Supply routing fix - Added bulk capacitors for FPGA - Minor footprint correction (thermal pad on clock IC…) 7/11

Ongoing test Up to 8 Gbps rate with no error Different speed is possibile

Ongoing test Up to 8 Gbps rate with no error Different speed is possibile only for different quad with Xilinx IBER Tool. A custom FW is under development to test the experiment link setup (7 x 1. 25 Gbps, 1 x 6. 25 Gbps) 8/11

K 7 Board v 2. 0 with blind via Final version of link board

K 7 Board v 2. 0 with blind via Final version of link board (K 7 Board v 2. 0) PCB was delivered last week. Differential line characterization is ongoing. Standard Via No Shield Blind Via No shield 9/11

FPGA Resources Total = 2, 501 W A lot of resources are available for

FPGA Resources Total = 2, 501 W A lot of resources are available for preliminary trigger analysis … 10/11

Next Steps - Three mounted K 7 Board v 2. 0 prototype (final version)

Next Steps - Three mounted K 7 Board v 2. 0 prototype (final version) will be delivered next week. - Mother board v 2. 1 prototype (final version) will be delivered before the end of November - Firmware development for link board is ongoing. - Slow control firmware for USOP board is ongoing. - We will be ready for production before the end of the year. 11/11

Thank you!

Thank you!