RISC vs CISC Dhiraj Parashar Shiva Prasad Behera
RISC vs. CISC Dhiraj Parashar Shiva Prasad Behera Vivek Sharma 10/7/2020 CS 654
Overview l Introduction l Key arguments l Comparisons l Post-RISC l Current Trends 10/7/2020 CS 654
CISC Evolution l Storage and Memory – High cost of memory. – Need for compact code. l Support for high-level languages l Ease of adding new microinstructions l Marketing Strategy 10/7/2020 CS 654
CISC Effects l Moved complexity from s/w to h/w l Compact code l Ease of compiler design (HLLCA) l Easier to debug l Lengthened design times l Increased design errors 10/7/2020 CS 654
RISC Evolution l Increasingly cheap memory l Improvement in compiler technology Patterson: “Make the common case fast” 10/7/2020 CS 654
RISC Effect l Move complexity from h/w to s/w l Provided a single-chip solution l Better use of chip area l Better Speed l Feasibility of pipelining – Single cycle execution stages – Uniform Instruction Format 10/7/2020 CS 654
Key arguments l RISC argument – for a given technology, RISC implementation will be faster – current VLSI technology enables single-chip RISC – when technology enables single-chip CISC, RISC will be pipelined – when technology enables pipelined CISC, RISC will have caches l CISC argument – CISC flaws not fundamental (fixed with more transistors) – Moore’s Law will narrow the RISC/CISC gap (true) – software costs will dominate (very true) 10/7/2020 CS 654
Role of Compiler: RISC vs. CISC instruction: MUL <addr 1>, <addr 2> l RISC instructions: LOAD A, <addr 1> LOAD B, <addr 2> MUL A, B STORE <addr 1> l RISC is dependent on optimizing compilers l 10/7/2020 CS 654
Comparisons l The Case for RISC (1980) – Introductory paper advocating RISC l Colwell et al. (1985) – Comparison studies misleading – Envisions use of techniques from both l Clark, Bhandarkar (1990) – MIPS M/2000 vs. VAX 8700 – Unfair comparison (? !) 10/7/2020 CS 654
Post-RISC Architecture l Additional functional units for superscalar l Additional “non-RISC” (but fast) instructions l Increased pipeline depth l Branch prediction l Out of order execution 10/7/2020 CS 654
Current Trends l P 6 - x 86 instructions decoded into RISClike instructions (ROps) Intel called this hack CRISC. This concept was so moronic that even Intel could not market it! l IA-64 - dependence on compilers for scheduling l Athlon – both direct execution and microprogrammed instructions 10/7/2020 CS 654
Thanks! 10/7/2020 CS 654
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