RIBF DAQ Hidetada Baba Topics FPGA Time stamp
RIBF DAQ Hidetada Baba
Topics • • FPGA Time stamp Dead time Cluster storage
Basic concept Multi crate (multi FEC) - Parallel readout = dead-time reduction - Online full event building (for common trigger) Common trigger (as far as possible) + Individual trigger (with time-stamp)
Big. RIPS FEC (10 x. FEC) Common trigger F 11 d. E, E CAMAC CC/7700 F 9 -F 11 Pl/PPAC T CAMAC CC/NET Isomer F 7 d. E CAMAC CC/7700 F 7 Ge CAMAC CC/7700 F 3 d. E CAMAC CC/7700 B 2 F F 1 -F 4, F 6 Pl/PPAC CAMAC CC/NET Master Event Builder d 02 F 9 -F 11 Pl/PPAC Q CAMAC CC/NET Analysis server a 02 SSM Scaler VME CPU F 5 Pl/PPAC F 7 Pl/PPAC CAMAC CC/NET F 8 Pl/PPAC CAMAC CC/NET B 3 F
Big. RIPS+DALI DAQ Common trigger F 11 d. E, E CAMAC CC/7700 F 9 -F 11 Pl/PPAC T CAMAC CC/NET F 9 -F 11 Pl/PPAC Q CAMAC CC/NET F 8 DALI VME Isomer F 7 Ge CAMAC CC/7700 F 7 d. E CAMAC CC/7700 F 3 d. E CAMAC CC/7700 B 2 F F 1 -F 4, F 6 Pl/PPAC CAMAC CC/NET Master Event Builder d 02 F 5 Pl/PPAC F 7 Pl/PPAC CAMAC CC/NET F 8 Pl/PPAC CAMAC CC/NET B 3 F
Dead Time (Big. RIPS) • 150 -- 170 us/event • for CC/NET • • Gate Conversion Interrupt Readout = 0. 1 -- 10 us = 25 us = 30 us ~ 100 us – (CAMAC 80 us)
with SHARAQ (Nov. 09) SHARAQ Beam shvmif 3 shvmih 7 shvmif 6 shd 01 CCEB Server VMIVME (FEC) shssm + TSM CC/NET (FEC) CC Domain Ethernet shvmihx shvmih 9 ccnet 01 + TSM SAN ccnet 02 GFS d 02 CCEB shvmis 2 + TSM ssm Big. RIPS d 01 AUEB SHARAQ S 2 a 02 TSEB ANAPAW Timestamp-based Event building
for beta-decay (Nov. 2009) Big. RIPS + RI BGO Beta Ge Ext 3 Ge(DSP) Ext 3 GFS TSEB+ Analysis
For you • I don’t want to tune the fine timing for each experiment • I need second/minutes range TDC • I don’t need coincident with beam • Measure Isomer without disturbing other trigger • Connect with other facility's DAQ system
Time stamp event build (in progress) Detector section Group A Detector section Group B Trigger A Time stamp 100 MHz, 48 bits
Time stamp event build (in progress) Big. RIPS DAQ FEC FEC FEC EB Beam trigger Gamma DAQ FEC EB Gamma single trigger Time stamp 100 MHz, 48 bits
Time stamp based event build • Timing histogram relative to Beam timing Beam • Coincidence window (Offset and Width) Gamma is set by human hands = Software coincidence Neutron 0 Offset Width Time difference We can change the coincidence configuration after experiments
Example (Beta decay) T 0 = beta and veto beta and techno beta and beam
Example (Beta decay) beam and beta beam and veto beam and techno T 0 = beam
Example (Beta decay) T 0 = beta and veto and beam beta and techno and beam beta and beam
Example (Beta decay) T 0 = beta and veto not beam beta and techno not beam beta and beam
Time stamp module • CAMAC and VME – – Based on FPGA Not only for the time stamp Output, Interrupt, Coincidence register G. G. , Scaler, and so on…
FPGA + CAMAC/VME Interface 8 LED CAMAC Interface (CPLD) CAMAC Bus Internal Oscillator (50 MHz) User FPGA (Spartan 3 E) 4 NIM IN 16 LVDS / 32 LVTTL IN/OUT 4 NIM OUT
VME module 8 LED VME Interface (CPLD) 4 NIM IN 16 LVDS / 32 LVTTL IN/OUT 4 NIM OUT User FPGA (Spartan 3 E)
Time Stamp: Clock synchronization FPGA 25 MHz Clock DLL 100 MHz clock 25 MHz Clock Through out Clear Counter 48 bits depth Trigger FIFO Memory Oct. 14, 2009 Hawaii Hidetada Baba @ RIKEN VME/CAMAC 20
Time stamp stability • Counting loss = 0 – For the moment – Error monitoring mechanism would be better to implement. . . • Power off, Cable remove. . .
Time Stamp Event Builder FEC Ether FEC EB SAN EB Raw Data TS Table TSEB Data Shared storage = SAN + Redhat GFS off-line analysis Analyzer on-line analysis
Not only for time-stamp • • Already done Programmable G. G. (clock sync. ) Trigger selector with VETO Coincidence register Output register (clock sync. ) Interrupt register with delay (clock sync. ) NIM <-> LVDS converter Timestamp with FIFO • • Next try Scaler, preset scaler, rate divider DMA TDC ! • Time stamp • Output register • Interrupt register 20 man en, CAMAC, VME
Development span • March • April-May • May-June decided to develop specification order – from IT division, 240 man en – other labs, 20 man en / module • End of September • End of October delivery First experiment – Big. RIPS + SHARAQ • End of November – Beta decay Second experiment
Dead Time (SHARAQ) • Big. RIPS • SHARAQ BLD • SHARAQ S 2 200? us/event < 100 us/event 500? us/event – Trigger rate = << 100 cps • For physics = S 2 only (> 90%) • For beam profile = Big. RIPS + BLD + S 2 – << 10%
Good example (Beam trigger) Big. RIPS SHARAQ BLD SHARAQ S 2 Time stamp
Good example (Beam trigger) 1000000 / 1000000 Big. RIPS 60000 / 85000 SHARAQ BLD 60 / 2000 Coincidence = Accepted 3% SHARAQ S 2 Time stamp
Dead time simulation 2 DAQ system (CAMAC) Common trigger, non dead-time sharing
Dead time simulation 2 DAQ system Beam DAQ = Beam x gamma trigger = 1 kcps fix (CAMAC) Gamma DAQ = Gamma trigger = 0 to 100 kcps V 792 + V 775 (Event by event readout vs Multi event buffer)
Dead time simulation 2 DAQ system Beam DAQ = Beam x gamma trigger = 1 kcps fix Gamma DAQ = Gamma trigger = 0 to 100 kcps QTC + CAEN V 1190
Dead time monitor • 1 dead time free system – Collect all trigger time-stamp • Off-line analysis – Dead time = depends on DAQ combination Big. RIPS Beta BGO Clover
Time stamp • Short dead time ! – Low trigger rate – Fast readout • Dead time – Simulation – Dead time monitor
To do / in progress list • Software – Bug fix (device driver / DAQ controller) – CBLT (VME) – GUI DAQ controller – On-line time stamp event building • Hardware – Monitor/correction mechanism for time stamp – Precise time stamp timing (<< 10 ns) • Performance measurement
Collaboration • MUST 2 DAQ + RIBF DAQ – with GANIL engineer – Common trigger – Data format + run command translator • Munchen group (beta decay) – Time stamp – Data format ? • New analysis software – Ota (CNS), Takeuchi, Ohnishi, Isobe, Baba
Future / more man power • DSP de PID • Level 2? trigger – Data reduction – Trigger via Ethernet • Absolute time stamp ?
Discussion • Organization ? – – – Detector DAQ hardware DAQ software Analysis Infrastructure User support • Budget – Infrastructure • Maintenance fee – Development • Short range • Long term
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