RF Pulse Modulation and the Digitally Driven Class

RF Pulse Modulation and the Digitally Driven Class C Power Amplifier R. Uang, J. Keyzer, A. Dalvi, Y. Sugiyama, M. Iwamoto, I. Galton and P. Asbeck, UCSD High Speed Devices Group

Introduction • Digital RF generation – DSP’s are approaching the microwave regime: • Intel Pentium 4 ALU operates at 4 GHz. – CMOS processes continue to be scaled in size, reducing power and increasing speed. • We can use digital RF to improve modern wireless communication systems by: – Reducing power dissipation using high efficiency power amplifiers. – Using DSP to generate signals such that system can overcome limitations of PA alone. – Developing versatile “mostly-CMOS” transmitters with programmable functionality. High Speed Devices Group

Overview • System Overview – RF Digital Pulsewidth Modulation • The Digitally Driven Class C Power Amplifier • Simulations and Experimental Results • Conclusions High Speed Devices Group

Future RF Transmitters Present Microwave Transmitter Future Microwave Transmitter f. IF(cos) I DSP Q DAC + Filter I DSP Q x Filter VGA PA x fo f. IF(sin) fbb=fs/N High Speed Devices Group x Digital Upconverter fclk D-S Pulse Modulator x 8 DSP PA Analog filter

Concept: Digital D-S RF Pulse Modulation Desired RF signal with AM and PM RF pulse modulated waveform D-S RF pulse modulated waveform High Speed Devices Group

Concept: Digital D-S RF Pulse Modulation 1 (Pulse Wdith) 3 1 RF(t) t 3 4 (Pulse Position) High Speed Devices Group 6

D-S Pulse Modulator Block Diagram Phase Modulation fclk DS Modulator fin(t) Envelope Modulation Ain(t) 3 Bit Word Pulse Generator fclk DS Modulator 1. 5 Bit Word Digital pulse Position Modulator Digital Pulse Width Modulator 8 fclk High Speed Devices Group RF Output

Simulations Single Tone • Single tone: spur level typically below - 55 d. Bc in desired band. • Delta-Sigma modulator shapes quantization noise away from signal of interest. CDMA (broad band view) CDMA: Linearity Test Meets IS-95 ACPR Specs High Speed Devices Group

The Digitally Driven Class C Power Amplifier Vdd RFC Shunt LC Resonator Vin ID RF Pulse Digital Input • • L Vout C Ga. As. FET t Load Replace modulated sinusoidal input with RF digital pulse modulated signal • Input is digital pulse train with varying pulse width and position • ID assumes pulse shape Desired output is modulated sinusoid High Speed Devices Group t

Digitally Driven Class C PA - Analysis Efficiency and Output Power vs. Conduction Angle Imax 0 VD T/4 T/2 T t Vdd Vmin 0 π 2π ωt Power at fundamental (W) 0. 5 ID 0. 4 Traditional PA Pout Drain Efficiency 70 0. 3 60 50 0. 2 40 Drain Efficiency Pout Digitally Driven PA Class C 0. 1 360 High Speed Devices Group 90 80 0 @ 100 315 270 225 180 135 90 45 Conduction Angle (Degrees) 30 20 10 0 0 Drain Efficiency (%) W < T/2

Simulated PA Performance: RL, opt 3’s 0. 30 0. 25 0. 20 Rlopt for 3’s 0. 15 0. 10 0. 05 0. 00 1’s 0 10 20 30 40 70 Drain Efficiency Power of fundamental (W) Power of fundamental vs. Load Resistance 0. 35 60 70 80 90 Rl Pattern Rlopt ADS Rlopt Analysis 1’s 49Ω 41Ω 3’s 16Ω 13Ω Rl, opt coincides with max voltage swing at output, max power at fundamental. High Speed Devices Group 60 3’s 50 40 30 1’s 20 10 Rlopt for 1’s 50 Drain Efficiency vs. Load Resistance 100 0 0 10 20 30 40 50 60 70 80 90 100 Rl • • Peak efficiency does not occur at fixed Rl for varying pulse widths. Optimum load occurs before maximum drain efficiency is reached.

Experimental Test Setup Conexant CX 60061 OC-192 Serializer HP 16522 A Pattern Generator Matlab Generated Sequences 16 bits 16: 1 Class C PA under testing 1 bit 3. 2 Gbps 200 Mbps Conexant CX 60077 Laser Driver Amplified Output Synchronized 200 MHz / 3. 2 GHz Clocks • Pattern generator outputs looping bit sequence • Serializer multiplexes to high data rate (3. 2 Gbps), 900 m. V signal swing • Laser driver amplifies signal 2 x to 2. 5 V max swing (adjustable) High Speed Devices Group

Experimental Results: Pulse Train Prototype Class C PA Drain Efficiency Pattern • • Calculated Simulated 1’s 73% 55% 39% 3’s 59% 63% 74. 5% Measured efficiency for 3’s exceeds calculated value. Measured efficiency for 1’s is much less than expected. Switching Mode Drain Efficiency 100 Drain Efficiency vs. Output Power for ideal amplifiers with modulated signals Digitally Driven Class C 80 Class B 60 Class A 40 20 0 0 0. 1 0. 2 0. 3 0. 4 0. 5 0. 6 0. 7 Pout (Normalized) High Speed Devices Group Measured 0. 8 0. 9 1

Experimental Results: CDMA Linearity Results to Date Input to PA Output 5 d. B/div 30 k. Hz BW “CDMA” signal - OQPSK at 400 MHz Po = +17. 1 d. Bm, 22% Drain Efficiency IS-95 ACPR specifications overlaid in red High Speed Devices Group 5 d. B/div 30 k. Hz BW

Conclusions • A novel Digitally Driven Class C Power Amplifier has been demonstrated using a commercial power Ga. As. FET. • This new variant of the Class C PA presents many unique challenges in its design and implementation. • RF Digital Pulsewidth Modulation combined with the Digitally Driven Class C Power Amplifier may potentially provide a means for high efficiency, high linearity, easily reconfigured RF and microwave transmitters. High Speed Devices Group

Simulated PA Performance: RL, opt 3’s 0. 30 including package model 0. 25 0. 20 Rlopt for 3’s 0. 15 0. 10 0. 05 0. 00 1’s 0 10 20 30 40 60 70 80 90 Rl Pattern Rlopt ADS Rlopt Analysis 1’s 49Ω 41Ω 3’s 16Ω 13Ω Rl, opt coincides with max voltage swing at output, max power at fundamental. High Speed Devices Group Drain Efficiency vs. Load Resistance 60 50 3’s 40 100 including package model 30 20 1’s 10 Rlopt for 1’s 50 70 Drain Efficiency Power of fundamental (W) Power of fundamental vs. Load Resistance 0. 35 0 0 10 20 30 40 50 60 70 80 90 100 Rl • • Peak efficiency does not occur at fixed Rl for varying pulse widths. Optimum load occurs before maximum drain efficiency is reached.