Review MIPS Pipeline Data and Control Paths PCSrc

Review: MIPS Pipeline Data and Control Paths PCSrc ID/EX EX/MEM Control IF/ID Add Reg. Write 4 PC Instruction Memory Read Address Shift left 2 Read Addr 1 Read Addr 2 Data 1 File Write Addr 16 Sign Extend MEM/WB Branch Data Memory Register Read Write Data ALUSrc ALU Read Data 2 Address Read Data Write Data ALU cntrl 32 ALUOp Reg. Dst Overcoming Data Hazards Add Mem. Write Mem. Read Memto. Reg

Review: Another Way to “Fix” a Data Hazard or $8, $1 sw $4, 4($1) Overcoming Data Hazards IM Reg DM IM Reg ALU and $6, $7, $1 DM ALU sub $4, $1, $5 Reg ALU IM ALU O r d e r add $1, ALU I n s t r. Fix data hazards by forwarding results as soon as they are available to where they are Reg needed Reg Reg DM Reg

Data Forwarding (aka Bypassing) q Take the result from the earliest point that it exists in any of the pipeline state registers and forward it to the functional units (e. g. , the ALU) that need it that cycle q For ALU functional unit: the inputs can come from any pipeline register rather than just from ID/EX by l adding multiplexors to the inputs of the ALU l connecting the Rd write data in EX/MEM or MEM/WB to either (or both) of the EX’s stage Rs and Rt ALU mux inputs l adding the proper control hardware to control the new muxes Overcoming Data Hazards

Data Forwarding Control Conditions 1. EX/MEM hazard: if (EX/MEM. Reg. Write and (EX/MEM. Register. Rd Forward. A = 10 if (EX/MEM. Reg. Write and (EX/MEM. Register. Rd Forward. B = 10 2. != 0) = ID/EX. Register. Rs)) != 0) = ID/EX. Register. Rt)) Forwards the result from the previous instr. to either input of the ALU MEM/WB hazard: if (MEM/WB. Reg. Write and (MEM/WB. Register. Rd Forward. A = 01 if (MEM/WB. Reg. Write and (MEM/WB. Register. Rd Forward. B = 01 Overcoming Data Hazards != 0) = ID/EX. Register. Rs)) != 0) = ID/EX. Register. Rt)) Forwards the result from the second previous instr. to either input of the ALU

Forwarding Illustration sub $4, $1, $5 and $6, $7, $1 Reg DM IM Reg ALU IM ALU O r d e r add $1, ALU I n s t r. EX/MEM hazard forwarding Overcoming Data Hazards Reg DM Reg MEM/WB hazard forwarding

Yet Another Complication! add $1, $2 O r d e r add $1, $3 add $1, $4 Overcoming Data Hazards IM Reg DM IM Reg ALU I n s t r. ALU Another potential data hazard can occur when there is a conflict between the result of the WB stage instruction and the MEM stage instruction – which should be forwarded? ALU q Reg DM Reg

Corrected Data Forwarding Control Conditions 2. MEM/WB hazard: if (MEM/WB. Reg. Write and (MEM/WB. Register. Rd != 0) and (EX/MEM. Register. Rd != ID/EX. Register. Rs) and (MEM/WB. Register. Rd = ID/EX. Register. Rs)) Forward. A = 01 if (MEM/WB. Reg. Write and (MEM/WB. Register. Rd != 0) and (EX/MEM. Register. Rd != ID/EX. Register. Rt) and (MEM/WB. Register. Rd = ID/EX. Register. Rt)) Forward. B = 01 Overcoming Data Hazards

Datapath with Forwarding Hardware PCSrc ID/EX EX/MEM Control IF/ID Add Shift left 2 4 PC Instruction Memory Read Address Add Read Addr 1 Read Addr 2 Data 1 File Write Data 16 Sign Extend MEM/WB Data Memory Register Read Write Addr Branch ALU Read Data 2 Address Read Data Write Data ALU cntrl 32 EX/MEM. Register. Rd ID/EX. Register. Rt ID/EX. Register. Rs Overcoming Data Hazards Forward Unit MEM/WB. Register. Rd

Memory-to-Memory Copies q For loads immediately followed by stores (memory-tomemory copies) can avoid a stall by adding forwarding hardware from the MEM/WB register to the data memory input. l sw $1, 4($3) Overcoming Data Hazards IM Reg DM IM Reg ALU O r d e r lw $1, 4($2) ALU I n s t r. Would need to add a Forward Unit and a mux to the memory access stage Reg DM Reg

Forwarding with Load-use Data Hazards or xor $8, $1, $9 $4, $1, $5 xor $4, $1, $5 Overcoming Data Hazards Reg DM IM Reg ALU or $6, $1, $7 $8, $1, $9 and IM ALU and $4, $1, $5 $6, $1, $7 sub DM ALU stall $4, $1, $5 sub Reg ALU $1, 4($2)IM ALU O r d e r lw ALU I n s t r. Reg Reg Reg DM

Load-use Hazard Detection Unit q Need a Hazard detection Unit in the ID stage that inserts a stall between the load and its use ID Hazard Detection if (ID/EX. Mem. Read and ((ID/EX. Register. Rt = IF/ID. Register. Rs) or (ID/EX. Register. Rt = IF/ID. Register. Rt))) stall the pipeline 2. q The first line tests to see if the instruction now in the EX stage is a lw; the next two lines check to see if the destination register of the lw matches either source register of the instruction in the ID stage (the load-use instruction) q After this one cycle stall, the forwarding logic can handle the remaining data hazards Overcoming Data Hazards

Stall Hardware q Along with the Hazard Unit, we have to implement the stall q Prevent the instructions in the IF and ID stages from progressing down the pipeline – done by preventing the PC register and the IF/ID pipeline register from changing l q Insert a “bubble” between the lw instruction (in the EX stage) and the load-use instruction (in the ID stage) (i. e. , insert a noop in the execution stream) l q Hazard detection Unit controls the writing of the PC (PC. write) and IF/ID (IF/ID. write) registers Set the control bits in the EX, MEM, and WB control fields of the ID/EX pipeline register to 0 (noop). The Hazard Unit controls the mux that chooses between the real control values and the 0’s. Let the lw instruction and the instructions after it in the pipeline (before it in the code) proceed normally down the pipeline Overcoming Data Hazards

Adding the Hazard Hardware PCSrc Hazard Unit EX/MEM 0 Control 0 Shift left 2 4 Instruction Memory PC ID/EX. Mem. Read 1 IF/ID Add ID/EX Read Address Read Addr 1 Read Addr 2 Data 1 File Write Addr 16 Sign Extend Read Data 2 32 ID/EX. Register. Rt Branch Data Memory Register Read Write Data Overcoming Data Hazards Add ALU Address Read Data Write Data ALU cntrl Forward Unit MEM/WB