reset clk rst clk2 2 Divider clk4 4

除頻器振盪器頻率 reset clk ○ rst clk_2 除 2 Divider clk_4 除 4 clk_8

除頻程式範例 module div(clk, rst, clk_2, clk_4, clk_8); input clk, rst; output clk_2, clk_4, clk_8;

Pin & Location Assignments set_location_assignment set_location_assignment PIN_29 -to clk PIN_165 -to clk_1 PIN_166 -to

修改後程式 module div(clk, rst, clk_2, clk_4, clk_8); input clk, rst; output clk_2, clk_4, clk_8;

Homework Design a clock divider to divide a clock frequency by 10. (以LED 1顯示原頻率，以LED

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除頻器振盪器頻率 reset clk ○ rst clk_2 除 2 Divider clk_4 除 4 clk_8 除 8

除頻程式範例 module div(clk, rst, clk_2, clk_4, clk_8); input clk, rst; output clk_2, clk_4, clk_8; reg cnt 2; reg [1: 0]cnt 4; reg [2: 0]cnt 8; wire clk_2, clk_4, clk_8; always @ (posedge clk or negedge rst) if (!rst) begin cnt 2<=0; cnt 4<=0; cnt 8<=0; end else begin cnt 2<=cnt 2+1; cnt 4<=cnt 4+1; cnt 8<=cnt 8+1; end assign clk_2=cnt 2; assign clk_4=cnt 4[1]; assign clk_8=cnt 8[2]; endmodule

Pin & Location Assignments set_location_assignment set_location_assignment PIN_29 -to clk PIN_165 -to clk_1 PIN_166 -to clk_2 PIN_167 -to clk_4 PIN_168 -to clk_8 PIN_240 -to rst Note: 程式須要修改增加clk_1(原頻率）

修改後程式 module div(clk, rst, clk_2, clk_4, clk_8); input clk, rst; output clk_2, clk_4, clk_8; reg cnt 2; reg [1: 0]cnt 4; reg [2: 0]cnt 8; wire clk_2, clk_4, clk_8; always @ (posedge clk or negedge rst) if (!rst) begin cnt 2<=0; cnt 4<=0; cnt 8<=0; end else begin cnt 2<=cnt 2+1; cnt 4<=cnt 4+1; cnt 8<=cnt 8+1; end assign clk_1=rst&clk; assign clk_2=cnt 2; assign clk_4=cnt 4[1]; assign clk_8=cnt 8[2]; endmodule

Homework Design a clock divider to divide a clock frequency by 10. (以LED 1顯示原頻率，以LED 2顯示除頻後頻率） o