Registers Register a collection of binary storage elements

Registers • Register – a collection of binary storage elements • In theory, a register is sequential logic which can be defined by a state table • More often think of a register as storing a vector of binary values • Frequently used to perform simple data storage and data movement and processing operations 1 KU College of Engineering Elec 204: Digital Systems Design 1

Example: 2 -bit Register • How many states are there? • How many input combinations? Output combinations • What is the output function? • What is the next state function? • Moore or Mealy? In 1 C In 0 2 D Q CP Current State • What are the quantities above for an n-bit register? D Q A 1 A 0 0 1 1 A 0 Y 1 Y 0 C Next State A 1(t+1) A 0(t+1) For I 1 I 0 = 00 01 10 11 00 01 10 11 KU College of Engineering Elec 204: Digital Systems Design A 1 Output (=A 1 A 0) Y 1 0 0 1 1 Y 0 0 1 2

Register Design Models • Due to the large numbers of states and input combinations as n becomes large, the state diagram/state table model is not feasible! • What are methods we can use to design registers? – Add predefined combinational circuits to registers • Example: To count up, connect the register flip-flops to an incrementer – Design individual cells using the state diagram/state table model and combine them into a register • A 1 -bit cell has just two states • Output is usually the state variable 3 KU College of Engineering Elec 204: Digital Systems Design 3

Register Storage • Expectations: – A register can store information for multiple clock cycles – To “store” or “load” information should be controlled by a signal • Reality: – A D flip-flop register loads information on every clock cycle • Realizing expectations: – Use a signal to block the clock to the register, – Use a signal to control feedback of the output of the register back to its inputs, or – Use other SR or JK flip-flops which for (0, 0) applied store their state • Load is a frequent name for the signal that controls register storage and loading – Load = 1: Load the values on the data inputs – Load = 0: Store the values in the register 4 KU College of Engineering Elec 204: Digital Systems Design 4

Registers with Clock Gating • Load signal is used to enable the clock signal to pass through if 1 and prevent the clock signal from passing through if 0. • Example: For Positive Edge-Triggered or Negative Pulse Master-Slave Flip -flop: Clock Load Gated Clock to FF • What logic is needed for gating? • What is the problem? Gated Clock = Clock + Load Clock Skew of gated clocks with respect to clock or each other 5 KU College of Engineering Elec 204: Digital Systems Design 5

Registers with Load-Controlled Feedback • A more reliable way to selectively load a register: – Run the clock continuously, and • • 6 – Selectively use a load control to change the register contents. Example: 2 -bit register 2 -to-1 Multiplexers with Load Control: For Load = 0, loads register contents (hold current values) A 1 Y 1 D Q For Load = 1, Load loads input values In 1 C (load new values) Hardware more complex A 0 than clock gating, but Y 0 D Q C free of timing problems In 0 Clock KU College of Engineering Elec 204: Digital Systems Design 6

Register Transfer Operations • Register Transfer Operations – The movement and processing of data stored in registers • Three basic components: – set of registers – operations – control of operations • Elementary Operations -- load, count, shift, add, bitwise "OR", etc. – Elementary operations called microoperations 7 KU College of Engineering Elec 204: Digital Systems Design 7

Register Notation R 15 8 7 0 PC(H) PC(L) • • • 8 76543210 15 0 R 2 Letters and numbers – denotes a register (ex. R 2, PC, IR) Parentheses ( ) – denotes a range of register bits (ex. R 1(1), PC(7: 0), AR(L)) Arrow ( ) – denotes data transfer (ex. R 1 R 2, PC(L) R 0) Comma – separates parallel operations Brackets [ ] – Specifies a memory address (ex. R 0 M[AR], R 3 M[PC] ) KU College of Engineering Elec 204: Digital Systems Design 8

Conditional Transfer K 1 • If (K 1 =1) then (R 2 R 1) is shortened to K 1: (R 2 R 1) where K 1 is a control variable specifying a conditional execution of the microoperation. R 1 n Load R 2 Clock K 1 Transfer Occurs Here No Transfers Occur Here 9 KU College of Engineering Elec 204: Digital Systems Design 9

Microoperations • Logical Groupings: – – Transfer - move data from one set of registers to another Arithmetic - perform arithmetic on data in registers Logic - manipulate data or use bitwise logical operations Shift - shift data in registers Arithmetic operations + Addition – Subtraction * Multiplication / Division 10 Logical operations Logical OR Logical AND Logical Exclusive OR Not KU College of Engineering Elec 204: Digital Systems Design 10

Example Microoperations • Add the content of R 1 to the content of R 2 and place the result in R 1 + R 2 • Multiply the content of R 1 by the content of R 6 and place the result in PC. PC R 1 * R 6 • Exclusive OR the content of R 1 with the content of R 2 and place the result in R 1 R 2 11 KU College of Engineering Elec 204: Digital Systems Design 11

Example Microoperations (Continued) • Take the 1's Complement of the contents of R 2 and place it in the PC. • PC R 2 • On condition K 1 OR K 2, the content of R 1 is Logic bitwise Ored with the content of R 3 and the result placed in R 1. • (K 1 + K 2): R 1 R 3 • NOTE: "+" (as in K 1 + K 2) and means “OR. ” In R 1 + R 3, + means “plus. ” 12 KU College of Engineering Elec 204: Digital Systems Design 12

Control Expressions • The control expression for an operation appears to the left of the operation and is separated from it by a colon • Control expressions specify the logical condition for the operation to occur • Control expression values of: – Logic "1" -- the operation occurs. – Logic "0" -- the operation does not occur. 13 § Example: X K 1 : R 1 + R 2 + 1 § Variable K 1 enables the add or subtract operation. § If X =0, then X =1 so X K 1 = 1, activating the addition of R 1 and R 2. § If X = 1, then X K 1 = 1, activating the addition of R 1 and the two's complement of R 2 (subtract). KU College of Engineering Elec 204: Digital Systems Design 13

Arithmetic Microoperations • From Table 7 -3: Symbolic Designation R 0 R 1 + R 2 R 0 R 1 + 1 R 0 R 2 + R 1 + 1 R 1 – 1 Description Addition Ones Complement Two's Complement R 2 minus R 1 (2's Comp) Increment (count up) Decrement (count down) • Note that any register may be specified for source 1, source 2, or destination. • These simple microoperations operate on the whole word 14 KU College of Engineering Elec 204: Digital Systems Design 14

• Ex: – X’K 1: R 1 + R 2 – X K 1: R 1 + R 2’ + 1 • K 1: activates operation • X : picks add or subtr 15 KU College of Engineering Elec 204: Digital Systems Design 15

Logical Microoperations • From Table 7 -4: Symbolic Designation R 0 R 1 R 2 16 Description Bitwise NOT Bitwise OR (sets bits) Bitwise AND (clears bits) Bitwise EXOR (complements bits) KU College of Engineering Elec 204: Digital Systems Design 16

Logical Microoperations (continued) • Let R 1 = 1010, and R 2 = 11110000 • Then after the operation, R 0 becomes: 17 KU College of Engineering Elec 204: Digital Systems Design 17

Shift Microoperations • From Table 7 -5: • Let R 2 = 11001001 • Then after the operation, R 1 becomes: Symbolic Designation R 1 sl R 2 R 1 sr R 2 Description R 1 10010010 01100100 Operation R 1 sl R 2 R 1 sr R 2 Shift Left Shift Right § Note: These shifts "zero fill". Sometimes a separate flip-flop is used to provide the data shifted in, or to “catch” the data shifted out. § Other shifts are possible (rotates, arithmetic). 18 KU College of Engineering Elec 204: Digital Systems Design 18

Register Transfer Structures • Multiplexer-Based Transfers - Multiple inputs are selected by a multiplexer dedicated to the register • Bus-Based Transfers - Multiple inputs are selected by a shared multiplexer driving a bus that feeds inputs to multiple registers • Three-State Bus - Multiple inputs are selected by 3 -state drivers with outputs connected to a bus that feeds multiple registers • Other Transfer Structures - Use multiplexers, multiple buses, and combinations of all the above 19 KU College of Engineering Elec 204: Digital Systems Design 19

Multiplexer-Based Transfers • Multiplexers connected to register inputs produce flexible transfer structures (Note: Clocks are omitted for clarity) • The transfers are: K 1: R 0 R 1 K 2 K 1: R 0 R 2 Load K 2 R 2 K 1 n Load n S 0 MUX 1 Load n R 0 R 1 20 KU College of Engineering Elec 204: Digital Systems Design 20

Multiplexer and Bus-Based Transfers for Multiple Registers • Multiplexer dedicated to each register • Shared transfer paths for registers – A shared transfer object is a called a bus (Plural: buses) • Bus implementation using: – multiplexers – three-state nodes and drivers • In most cases, the number of bits is the length of the receiving register 21 KU College of Engineering Elec 204: Digital Systems Design 21

Multiplexer Approach • Uses an n-input multiplexer with a variety of transfer sources and functions 22 KU College of Engineering Elec 204: Digital Systems Design 22

Multiplexer Approach • Load enable by OR of control signals K 0, K 1, … Kn-1 - assumes no load for 00… 0 • Use: – Encoder + Multiplexer (shown) or – n x 2 AND-OR to select sources and/or transfer functions 23 KU College of Engineering Elec 204: Digital Systems Design 23

Dedicated MUX-Based Transfers L 0 S 0 • Multiplexer connected to each register input produces a very flexible transfer structure => • Characterize the simultaneous transfers possible with this structure. n 0 n 1 S n MUX R 0 L 1 S 1 n 0 n 1 S n MUX 24 0 n 1 KU College of Engineering Elec 204: Digital Systems Design S MUX Load R 1 L 2 S 2 n Load R 2 24

Multiplexer Bus L 0 • A single bus driven by a multiplexer lowers cost, but limits the available transfers => • Characterize the simultaneous transfers possible with this structure. • Characterize the cost savings compared to dedicated multiplexers n Load R 0 S 1 S 0 n S 1 S 0 0 n 1 n 2 L 1 n n MUX Load R 1 L 2 n Load R 2 25 KU College of Engineering Elec 204: Digital Systems Design 25

Three-State Bus • The 3 -input MUX can be replaced by a 3 -state node (bus) and 3 -state buffers. • Cost is further reduced, but transfers are limited • Characterize the simultaneous transfers possible with this structure. • Characterize the cost savings and compare • Other advantages? L 0 n Load R 0 n E 0 L 1 n Load R 1 n E 1 n L 2 Load R 2 n E 2 26 KU College of Engineering Elec 204: Digital Systems Design 26