Registers and Counters Chapter 5 Registers and Counters

Registers and Counters Chapter 5

Registers and Counters Registers and counters are sequential functional blocks made of FFs. • Registers are used for storing and manipulating data. • Counters are used for sequencing and controlling of operations.

Registers and Counters • Registers consist of set of FFs together with gates that implement their state transitions. • Counters are registers that go through a predetermined sequence of states upon the application of clock pulses.

Registers Gated clock input • Causes clock skews due to propagation delays

4 -Bit Register with Parallel Load

4 -Bit Shift Register

Serial Transfer

Serial Addition

Shift Register With Parallel Load

Bi-directional Shift Register with Parallel Load

4 -Bit Ripple Counter

4 -Bit Ripple Counter Downward counting can be achieved by connecting the complement of FF outputs to clock inputs or by using positive edge triggered FFs Ripple counters are asynchronous and with added logic may be unreliable and delay dependent.

Synchronous Binary Counters

JQ 3 = KQ 3 = Q 0. Q 1. Q 2. EN JQ 2 = KQ 2 = Q 0. Q 1. EN JQ 1 = KQ 1 = Q 0. EN JQ 0 = KQ 0 = EN

4 -Bit Binary Synchronous Counter JQ 0 = KQ 0 = EN JQ 1 = KQ 1 = Q 0. EN JQ 2 = KQ 2 = Q 0. Q 1. EN JQ 3 = KQ 3 = Q 0. Q 1. Q 2. EN

4 -Bit Binary Counter with D FFs DQ 0 = m(0, 2, 4, 6, 8, 10, 12, 14) DQ 1 = m(1, 2, 5, 6, 9, 10, 13, 14) DQ 2 = m(3, 4, 5, 6, 11, 12, 13, 14) DQ 3 = m(7, 8, 9, 10, 11, 12, 13, 14) DQ 0 = Q 0 EN DQ 1 = Q 1 (Q 0. EN) DQ 2 = Q 2 (Q 0. Q 1. EN) DQ 3 = Q 3 (Q 0. Q 1. Q 2. EN) DQi = Qi (Q 0. Q 1. Q 2. . . Qi-1. EN)

Serial and Parallel Counters

4 -Bit Binary Counter with Parallel Load

BCD Counter BCD counter can be obtained from 4 -bit counters with parallel load.

Designing a BCD Counter with T FFs TQ 1 = 1 TQ 2 = Q 1 Q 8’ TQ 4 = Q 1 Q 2 TQ 8 = Q 1 Q 8 + Q 1 Q 2 Q 4 Y = Q 1 Q 8

Counter with Arbitrary Count JA = B K A = B JB = C KB = 1 JC = B’ KC = 1

Homework Do problems 11, 14, 18, 22, 27 of chapter 5