RECONFIGURABLE PROCESSING AND AVIONICS SYSTEMS RUSS DUREN DEPARTMENT
RECONFIGURABLE PROCESSING AND AVIONICS SYSTEMS RUSS DUREN DEPARTMENT OF ENGINEERING Duren 1
RECONFIGURABLE COMPUTING Duren 2
WHAT IS RECONFIGURABLE COMPUTING? • STANDARD COMPUTERS PERFORM DIFFERENT TASKS BY CHANGING THE PROGRAM THAT THE COMPUTER EXECUTES • RECONFIGURABLE COMPUTERS ARE PROGRAMMED BY CHANGING THE HARDWARE THAT EXECUTES THE PROGRAM • TYPICALLY RECONFIGURABLE COMPUTERS DO BOTH – STANDARD PROGRAMS ARE EXECUTED BY A STANDARD PROCESSOR – RECONFIGURABLE HARDWARE IS USED TO ACCELERATE CRITICAL PORTIONS OF THE CODE • RECONFIGURABLE HARDWARE IS IMPLEMENTED USING FIELD PROGRAMMABLE GATE ARRAYS (FPGAs) Duren 3
XILINX FIELD PROGRAMMABLE GATE ARRAYS I/O Blocks (IOBs) Programmable Interconnect Configurable Logic Blocks (CLBs) Special Purpose Resources Duren 4
CONFIGURABLE LOGIC BLOCKS (CLBs) u BASIC RESOURCE UNIT IS THE SLICE – 1 CLB CONTAINS 4 LOGIC CELLS u SLICE = 4 -INPUT LOOK-UP TABLE (LUT) + D FLIP-FLOP – LUT CAPACITY LIMITED BY NUMBER OF INPUTS, NOT COMPLEXITY OF FUNCTION – LUTS CAN BE USED AS LOGIC, RAM, OR ROM LUT Duren FF 5
ADDITIONAL RESOURCES • • INPUT/OUTPUT BLOCKS (IOBS) PROGRAMMABLE INTERCONNECT DELAY-LOCKED LOOPS (DLLS) BLOCK RAM FAST CARRY LOGIC MULTIPLIERS 36 Bit 18 Bit XC 2 V 6000 VIRTEX II FPGA – – 18 Bit 33, 792 SLICES 2, 592 Kbits of BLOCK RAM Signed Multiply Performance 144 18 -bit MULTIPLIERS 18 x 18 140 MHz AT 140 MHz > 25 BILLION MULTIPLIES/SEC 12 x 12 170 MHz 8 x 8 4 x 4 Duren 6 210 MHz 255 MHz Preliminary V 1. 60 Speeds File
PROCESSING SPEED IMPROVEMENTS • RECONFIGURABLE COMPUTERS USE FPGAS TO INCREASE PROCESSING SPEED BY: • USING CUSTOM HARDWARE TO COMPUTE RESULTS QUICKLY • USING PARALLEL CIRCUITRY TO COMPUTE MULTIPLE ANSWERS SIMULTANEOUSLY • USING PIPELINING TO INCREASE THROUGHPUT – ASSEMBLY LINE COMPUTATIONS • LATENCY • THROUGHPUT Duren 7
SRC-6 E Microprocessor Chassis MAP Chassis Duren 8
SRC-6 E m. P Chassis P 3 m. P (1000 MHz) 800* 8000 MAP Chassis Cache 800 Controller MIOC PCI-X Slots S N A P On-Board Memory (24 MB) 4800 (6 x 800) Duren 2400 MIOC 4800 (6 x 800) On-Board Memory (24 MB) User Logic 800 Controller 4800 (6 x 800) Memory (1. 5 GB) Cache S N A P Memory (1. 5 GB) 4800 (6 x 800) User Logic 9 2400 User Logic * Peak Theoretical 315 MB/s Write 195 MB/s Read PCI-X Slots
MAP Dual Processor Control Logic – – DMA engine Controls User Logic – – 2 Virtex II - 6 M gates each 100 -MHz clock Chain Port MAP/SNAP Cable Connectors Duren Chain Port On-Board Memory – – – 10 Board 18 in x 13 in 6 dual-ported memory banks 24 M bytes 64 b data paths
SRC-6 E PROGRAMMING ENVIRONMENT • PENTIUM PROCESSORS – LINUX OPERATING SYSTEM IS THE MAIN USER INTERFACE – C AND FORTRAN COMPILERS FOR CODE DEVELOPMENT – INTEL AND GNU COMPILERS SUPPORTED • FPGAS – SRC-6 E CUSTOM COMPILER CONVERTS HLL TO FPGA CIRCUITRY – FPGA ROUTINES WRITTEN IN C OR FORTRAN • SOFTWARE GENERATES ONE EXECUTABLE RESULT Duren 11
HARDWARE COMPILER • SRC COMPILER TRANSLATES THE C SOURCE INTO PIPELINED FPGA CIRCUITRY • FPGAS ARE CLOCKED AT 100 MHz • ONCE THE PIPELINE IS FILLED (LATENCY) RESULTS ARE PRODUCED EVERY 10 NANOSECONDS • IMPLEMENTS PARALLEL CIRCUITRY FOR INDEPENDENT STATEMENTS A(n) A(n+1) A(n+2) A(n+3) Duren = = my_func(X(n), Y(n)) my_func(X(n+1), Y(n+1)) my_func(X(n+2), Y(n+2)) my_func(X(n+3), Y(n+3)) 12
LIMITATIONS IMPOSED ON HLL ROUTINES • VERSION 1. 3 SUPPORTS: – – – – • DATA TYPES: 32 -BIT (INT) AND 64 -BIT (LONG) ADD, SUBTRACT, MULTIPLY DIVISION (32 -BIT ONLY) RELATIONAL OPERATORS (==, !=, <, >, <=, >=) BITWISE OPERATORS AND SHIFTS (&, |, !, <<, >>) LOGICAL OPERATORS (&&, !, ||) SQRT() (32 BIT ONLY) SOME RESTRICTIONS ON VARIABLE ACCESS AND CONTROL STATEMENTS – NOT PARTICULARLY LIMITING, BUT MUST BE CONSIDERED – EXAMPLE: NUMBER OF DATA WORDS TRANSFERRED MUST BE MULTIPLE OF 4 • FUTURE VERSIONS OF THE COMPILER WILL SUPPORT MORE OPERATIONS AND DATA TYPES AND RELAX RESTRICTIONS Duren 13
RECONFIGURABLE RESEARCH TOPICS • APPLICATION DEVELOPMENT – FOR SRC-6 E – FOR MULTIPLE FPGAS • PLATFORM COMPARISON – SRC, STARBRIDGE, WILDFIRE, NASA CLUSTER WITH FPGA NODES • ALGORITHM CLASSIFICATION – WHAT ALGORITHMS ARE BEST SUITED TO FPGA? – MATCHING ALGORITHMS TO ARCHITECTURES AND VICE VERSA • COMBINING ADAPTABLE HARDWARE WITH ADAPTABLE ALGORITHMS – NEURAL NETWORKS, GENETIC ALGORITHMS • DESIGN OF A CUSTOM RECONFIGURABLE PLATFORM Duren 14
AVIONICS SYSTEMS Duren 15
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HUD MPD KEYPAD HOTAS DISPLAY CONTROLLER MISSION COMPUTER 1 MISSION COMPUTER 2 SMS INS/GPS FLIGHT CONTROLS RADAR/ SENSORS EW SYSTEMS Federated Avionics System Duren 17 STORES COMMS DATA LINK MIL-STD-1553 Data Bus
AVIONICS RESEARCH TOPICS • DATA COMPRESSION ROUTINES FOR REAL-TIME, EMBEDDED, DEMAND-OPERATED SYSTEMS – SURVEY OF DATA TYPES AND TRANSMISSION RATES – SELECTION OF POTENTIAL COMPRESSION ROUTINES – ANALYSIS OF POTENTIAL BANDWIDTH SAVINGS • REAL-TIME SYSTEM ANALYSIS AND MODELING – EMERGING TOOLS FOR AVIONICS ARCHITECTURE MODELING AND ANALYSIS • SYSTEM OF SYSTEMS RESEARCH: HOW TO TAKE ADVANTAGE OF NETWORKED SYSTEMS – EXAMPLE: COMBAT ID - TARGET DETECTION, IDENTIFICATION, TRACKING, ELIMINATION OF MULTIPLE REPORTS Duren 18
RECONFIGURABLE AVIONICS SYSTEMS Duren 19
RECONFIGURABLE SATELLITE AVIONICS • NAVAL POSTGRADUATE SCHOOL CFTP PROGRAM – LAUNCHES SEPTEMBER 2006 – PC-104 IBM PERSONAL COMPUTER – CUSTOM RECONFIGURABLE PROCESSOR BOARD • DEMONSTRATE COMMERCIAL, OFF-THE-SHELF FPGA TECHNOLOGY APPLIED TO SPACECRAFT ARCHITECTURE AS A MEANS OF – DECREASING DEVELOPMENT TIME – DECREASING COSTS – INCREASING FLEXIBILITY AND RELIABILITY Duren 20
Configurable Fault Tolerant Processor Duren 21
NPS Configurable Fault Tolerant Processor (CFTP) • TRIPLE-REDUNDANT, FAULTTOLERANT RECONFIGURABLE SYSTEM -ON-A-CHIP (SOC) P EDAC memory voter P • DESIGN TO MITIGATE BIT ERRORS IN COMPUTATION BY DETECTING ERRORS AND CORRECTING THEM THROUGH VOTING LOGIC P Status I/O Duren 22
RECONFIGURABLE SPACE AVIONICS • RESEARCH OPPORTUNITIES – FAILURE ANALYSIS ON CURRENT DESIGN – ADDITIONAL EXPERIMENTS FOR RECONFIGURABLE BOARD • • ERROR DETECTION ERROR CORRECTION FAULT TOLERANT CIRCUITS PARTIAL FPGA RECONFIGURATION – TECHNIQUES FOR REMOTE DEBUGGING OF HARDWARE Duren 23
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