Reconfigurable HPC May 14 2004 TU Tallinn Estonia

Reconfigurable HPC May 14, 2004 , TU Tallinn, Estonia Reconfigurable HPC Reiner Hartenstein TU Kaiserslautern part 2 Data-Stream-based Computing

Preface TU Kaiserslautern Response to the Computenik Shock: the completely wrong roadmap to HPC. . . continue to bang their heads against the memory wall blinders to ignore the impact of morphware © 2004, reiner@hartenstein. de 2 instead of http: //hartenstein. de

Crusty Computing Sciences TU Kaiserslautern memory wall went morphware dead went morphware exhausted [David Padua, Hennessy] 98. 5% v. N-only this monopoly is the problem John © 2004, reiner@hartenstein. de 3 http: //hartenstein. de

Exhausted: Dead Supercomputer Society [Gordon Bell, keynote at ISCA 2000]. TU Kaiserslautern • ACRI • Alliant • American Supercomputer • Ametek • Applied Dynamics • Astronautics • BBN • CDC • Convex • Cray Computer • Cray Research • Culler-Harris • Culler Scientific • Cydrome • Dana/Ardent/ Stellar/Stardent © 2004, reiner@hartenstein. de • DAPP • Denelcor • Elexsi • ETA Systems • Evans and Sutherland • Computer • Floating Point Systems • Galaxy YH-1 • Goodyear Aerospace MPP • Gould NPL • Guiltech • ICL • Intel Scientific Computers • International Parallel Machines • Kendall Square Research • Key Computer Laboratories 4 • Mas. Par • Meiko • Multiflow • Myrias • Numerix • Prisma • Tera • Thinking Machines • Saxpy • Scientific Computer • Systems (SCS) • Soviet Supercomputers • Supertek • Supercomputer Systems • Suprenum • Vitesse Electronics http: //hartenstein. de

HPC going configware TU Kaiserslautern International Conference on Field-Programmable Logic and Applications (FPL) http: //fpl. org Aug. 20 – Sept 1, 2004, Antwerp, Belgium. . . going into every type of application µProc. accel. © 2004, reiner@hartenstein. de 288 submissions ! they all work on highhttp: //hartenstein. de performance 5

>> Machine vs. Anti Machine << TU Kaiserslautern • Machine vs. Anti Machine • Terminology • Morphware Platforms • coarse-grained Platforms • Dual Machine Paradigms http: //www. uni-kl. de © 2004, reiner@hartenstein. de • Final Remarks 6 http: //hartenstein. de

TU Kaiserslautern Reconfigurable Computing: a second programming domain Migration of programming to the structural domain The structural domain has become RAM-based The opportunity to introduce the structural domain to programmers. . . to bridge the gap by clever abstraction mechanisms using a simple new machine paradigm © 2004, reiner@hartenstein. de 7 http: //hartenstein. de

machine vs. anti machine TU Kaiserslautern CPU as. M matter vs. anti matter data stream machine data counter (anti machine) DPU as. M program counter (r)DPA without sequencer (r)DPA as. M . . . . RAM memory bank © 2004, reiner@hartenstein. de 8 . . . . as. M instruction stream machine (von Neumann etc. ) as. M: auto-sequencing Memory as. MA: auto-sequencing Memory Array http: //hartenstein. de

TU Kaiserslautern Data-stream-based Computing The Anti Universe of Computing © 2004, reiner@hartenstein. de 9

The anti universe TU Kaiserslautern • Paul Dirac predicted a complete anti universe consisting of antimatter • “There are regions in the universe, which consist of antimatter. . . • . . But there asymmetries” • when a particle hits antiparticle, both are converted into energy: Annihilation • We are not aware, that there is a new area in computing sciences , which consists of antimatter of computing • Reconfigurable Computing is made from this antimatter: data-stream-based computing © 2004, reiner@hartenstein. de 10 http: //hartenstein. de

anti particles TU Kaiserslautern • 1928: Paul Dirac: „there should be an anti electron having positive charge“ (Nobel price 1933) • 1932: Carl David Anderson detected this „positron“ in cosmic radiation (Nobel price 1936) hydrogen • 1954: new accelerators: cyclotron, like Berkeley‘s Bevatron anti hydrogen • 1955 Owen Chamberlain et al. create anti proton on Bevatron • 1956: anti neutron created on Bevatron • 1965: creation of a deuterium anti nucleus at CERN • 1995: hydrogen anti atom created at CERN – by forcing positron and anti proton to merge by very low energy. © 2004, reiner@hartenstein. de 11 http: //hartenstein. de

Matter & Antimatter: Atom and Anti Atom TU Kaiserslautern - + Anti Matter machine paradigm: Anti Atom g n i n n i p s n o r t c e l E - The World of Matter machine paradigm: the Atom P © 2004, reiner@hartenstein. de 12 + g n i n pin s n o r t i s o http: //hartenstein. de

Matter & Antimatter of Informatics : Machine and Anti Machine TU Kaiserslautern CPU - + m a e r t s n o i t c u r t s in g n i n n i p s Anti Machine paradigm 1936 1946 1971 1979 1990 1995 Machine paradigm: „von Neumann“ all ingred ien 1 st electronic computer (Konrad Zuse) v. N. machine paradigm 1 st microprocessor (Ted Hoff) „data streams“ (systolic array: Kung / Leiserson) anti machine paradigm published r. DPA / DPSS (supersystolic: Rainer Kress) novel compilation techniques ts availab le © 2004, reiner@hartenstein. de 13 DPU + - ng i n n i p s m a e r t s data http: //hartenstein. de

Matter vs. antimatter: CPU vs. DPU program counter © 2004, reiner@hartenstein. de instruction stream 14 - + + (r)DPA (r)DPU no CP U! CPU DPU + - + e r a es e ri r e et h t m m y as data streams stream CPU + + TU Kaiserslautern without sequencer http: //hartenstein. de

heavy anti atoms: DPA = DPU array coherent data streams spinning around TU Kaiserslautern + DPU - DPU DPU DPU DPA + + © 2004, reiner@hartenstein. de + + + - - - 15 - + DPA + - + http: //hartenstein. de

Terminology: DPU versus CPU. . . TU Kaiserslautern • • • DPU: data path unit DPA: DPU array GA: gate array r. DPU: reconfigurable DPU r. DPA: reconfigurable DPA r. GA: reconfigurable GA (r)DPU • DPU is no CPU: there is nothing central CPU - like in a DPA © 2004, reiner@hartenstein. de 16 DPU instruction sequencer http: //hartenstein. de

Parallelism by Concurrency TU Kaiserslautern independent instruction streams difficult. . . + + -

Annihilation? TU Kaiserslautern as h + cr - avoidable by careful methodology © 2004,

CS education. . . TU Kaiserslautern Configware / Software Co-Design? Hardware / Software Co-Design? Annihilation avoidable CS curricular revision © 2004, reiner@hartenstein. de An hardware person procedural nih ila tio n? structural by 19 software person http: //hartenstein. de

>> Terminology << TU Kaiserslautern • Machine vs. Anti Machine • Terminology • Morphware Platforms • coarse-grained Platforms • Dual Machine Paradigms http: //www. uni-kl. de © 2004, reiner@hartenstein. de • Final Remarks 20 http: //hartenstein. de

„Re-configurable Hardware“ ? ? TU Kaiserslautern Terminology has been highly confusing „Re-configurable Hardware“ ? ? this „Hardware“ is not hard ! it‘s Morphware We need a concise terminology: a consensus is on the way © 2004, reiner@hartenstein. de 21 http: //hartenstein. de

TU Kaiserslautern Configware and Flowware. . . are the sources for programming morphware. Software is the source for programming traditional hardwired processors (instruction-stream-driven: von Neumann machine paradigm and its derivatives) For Configware and Flowware we prefer the anti machine paradigm – conterpart of von Neumann © 2004, reiner@hartenstein. de 22 http: //hartenstein. de

de facto Duality of RAM-based platforms TU Kaiserslautern We now have 2 types of programmable platforms hardware viewed as frozen configware: Just earlier binding traditional RAM-based platform CPU „running“ on it: machine paradigm © 2004, reiner@hartenstein. de software 2 nd paradigm new morphware (FPGA, r. DPA. . ) configware von Neumann etc. : anti machine: instruction-stream-based data-stream-based 23 http: //hartenstein. de

TU Kaiserslautern Terminology: Digital System Platforms clearly distinguished source running on it platform hardware (not running on it) fine grain r. GA (FPGA) morphware coarse r. DPU, r. DPA grain reconfigurable data stream processor (hardwired) instruction stream processor © 2004, reiner@hartenstein. de machine paradigm configware flowware & configware flowware software 24 none anti machine von Neumann machine http: //hartenstein. de

TU Kaiserslautern Terminology: Digital System Platforms clearly distinguished source running on it platform hardware (not programmable) fine grain r. GA (FPGA) morphware coarse r. DPU, r. DPA grain reconfigurable data stream processor (hardwired) instruction stream processor © 2004, reiner@hartenstein. de machine paradigm configware flowware & configware flowware software 25 none anti machine von Neumann machine http: //hartenstein. de

Importance of binding time TU Kaiserslautern not all switching is done by Configware 0 c 1 time of e “instruction read new readrnew instruction a fetch” instructionw Microprocessor ft run time Parallel Computer So e r load time a w Reconfigurable for a pipe network g Configuration : like a i Computing f n kind of pre-packed compile time o configure C frozen-in „super datapaths instruction fetch“ fabrication time c cre a Fullw custom fabricate a datapath d ASIC oder r a http: //hartenstein. de © reiner@hartenstein. de 26 H 2004, 0 0 1 1

Software vs Flowware and Configware TU Kaiserslautern Programming source for instruction-stream-based computing (von Neumann etc. ): Software The programming source for data-stream-based computing operations (the anti machine paradigm): Flowware Programming sources for Reconfigurable Computing (morphware): µProc. d. schedule hdw. anti machine compile Flowware and Configware Sources for Embedded Systems: Flowware , Configware & Software © 2004, reiner@hartenstein. de compile 27 rec. anti machine partit. compiler µProc. rec. anti machine http: //hartenstein. de

control-procedural vs. data-procedural TU Kaiserslautern The structural domain is primarily data-stream-based: Flowware . . . mostly not yet modelled that way: most flowware is hidden by its indirect instruction-stream-based implementation Flowware converts „procedural vs. structural“ into „control-procedural vs. data-procedural“. . . © 2004, reiner@hartenstein. de 28 http: //hartenstein. de

TU Kaiserslautern Flowware Languages (Data Streaming Language examples) Brook : for modern graphics hardware DSP-C: allows to describe key features of DSPs www. dsp-c. org Streams-C: defines 1 -D streams; generates VHDL (LANL Open-source C compiler targets FPGAs) general purpose: Mo. PL: fully supporting the anti machine paradigm – the counterpart of the von Neumann paradigm © 2004, reiner@hartenstein. de 29 http: //hartenstein. de

programming: procedural vs. structural instruction-stream-based TU Kaiserslautern embedded systems: data-stream-based domain procedural structural computing in. . . time only* space and time hardwired program source software* „instruction“ fetch data „fetch“ not programmable fully hardwired: algorithms fixed resources fixed at runtime currently emerging (hardware +) software** flowware before fabrication reconfigurable configware + flowware at loading time at run time *) only one **) software „simulates“ flowware source needed reconfigurable: CPU: algorithms variable resources fixed © 2004, reiner@hartenstein. de 30 http: //hartenstein. de

TU Kaiserslautern approaching consensus digital system platforms: DPU data path unit r. DPU reconfigurable DPU DPA data path array (DPU array) r. DPA reconfigurable DPA ISP instruction set processor AM anti machine AMP data stream processor* r. AMP reconfigurable AMP *) no “dataflow machine” platform category hardware (not programmable) ISP** software • morphware configware data stream flowware processor (AMP*) reconfigurable categories of morphware: AMP (r. AMP) morphware use source „running“ on platform flowware & configware granularity (path width) • fine grain (FPGA) (~1 bit) coarse grain (e. g. 32 bits) reconfigurable computing multi granular: by slice bundling reconfigurable logic © 2004, reiner@hartenstein. de 31 Glossary machine paradigm none von Neumann FPGA: none anti machine (re)configurable blocks CLBs r. DPUs (e. g. ALU-like) r. DPU slices (e. g. 4 bits) **) Von Neumann etc. http: //hartenstein. de *) data stream processor

TU Kaiserslautern data streams*: not new 1980: data streams (Kung, Leiserson: systolic arrays) 1989: data-stream-based Xputer architecture e s u f n o tc ‘ n o d , “ e s w a o l e l f p a 1990: r. DPU (Rabaey) t *) a d „ h t wi 1994: Flowware Language Mo. PL (Becker et al. ) 1995: super systolic array (r. DPA) + DPSS tool (Kress) 1996+: Streams-C language, SCCC (Los Alamos), SCORE, ASPRC, Bee (UC Berkeley), DSP-C, Brook, . . . 1996: configware / software partitioning compiler (Becker) © 2004, reiner@hartenstein. de 32 http: //hartenstein. de

URLs: Software vs Flowware and Configware TU Kaiserslautern http: //morphware. net/ http: //configware. org/ http: //flowware. net/ http: //data-streams. org/ http: //anti-machine. org/ http: //kressarray. de/ compile µProc. d. schedule compile rec. anti machine , e s a e l p , s l a s o p o r p t e n d e. n m i e e v t o s n e t impr r a h @ to reiner ! r e t p a h c n w o r u o write y © 2004, reiner@hartenstein. de 33 hdw. anti machine partit. compiler µProc. rec. anti machine http: //hartenstein. de

>> Embedded Computing << TU Kaiserslautern • Machine vs. Anti Machine • Terminology • Morphware Platforms • coarse-grained Platforms • Dual Machine Paradigms http: //www. uni-kl. de © 2004, reiner@hartenstein. de • Final Remarks 34 http: //hartenstein. de

Fine-grain Morphware: Drawbacks TU Kaiserslautern • FPGA Architectures – SRAM-based Look-up Tables L( UTs) – Problems: • Routing: reduces Performance • Bad Ratio: active / passive Elements reconfigurable Interconnect (Switching Boxes) Configurable Logic Block (CLB) LUT © 2004, reiner@hartenstein. de 35 Source: R. Hartenstein http: //hartenstein. de

Reconfigurability Overhead TU Kaiserslautern area used by application partly for configuration code storage L L S L © 2004, reiner@hartenstein. de S L resources needed for reconfigurability “hidden RAM” not shown L S L 36 L L http: //hartenstein. de

Throughput vs. Efficiency TU Kaiserslautern MOPS / m. W 1000 L 100 d r a h 10 stan 0. 01 0. 001 a ur fig ble )* g n i ut p com ic g o l ) le b a SP r D u s A fig n ors o r. DP s c s e oce r s (r p A et s FPG n o i ssor e t c c o r ru icrop m d r inst da 0. 1 Wiring by abutment: 32 Bit example ed r i w n co e r ( 1 2 © 2004, reiner@hartenstein. de area used by application T. Claasen et al. : ISSCC 1999 *) R. Hartenstein: ISIS 1997 1 0. 5 37 0. 25 L S S L L L S L 1 Bit CLB L resources needed for reconfigurability 0. 13 0. 1 0, 07 µ feature size http: //hartenstein. de

One more argument for coarse grain TU Kaiserslautern T. Claasen et al. : ISSCC 1999 *) R. Hartenstein: ISIS 1997 MOPS / m. W 1000 100 i w d r ha 10 g tin u p m o c c) i g lo )* le b a SP r ( D u s A fig n ors o r. DP s c s e oce r s (r p A et s FPG n o i ssor e t c c o r ru icrop m d r inst da 0. 1 stan 0. 01 0. 001 ble a r gu fi on c e r 1 Wiring by abutment: a 32 Bit Kress. Array example red 2 © 2004, reiner@hartenstein. de 1 0. 5 0. 25 38 if coarse grain cells are full custom and mesh-connected, and 2 nd level interconnect ressources layouted over the cells the array is almost as area -efficient as hardwired 0. 13 0. 1 0, 07 µ feature size http: //hartenstein. de

It’s a Paradigm Shift ! TU Kaiserslautern • Using FPGAs (fine grain reconfigurable) just mainly has been classical Logic Synthesis on a “strange hardware” platform • Coarse Grain Reconfigurable Arrays (r. DPAs) (Reconfigurable Computing), however, mean a really fundamental Paradigm Shift • This is still ignored by CS and EE Curricula and almost all R&D scenes © 2004, reiner@hartenstein. de 39 http: //hartenstein. de

r. DPA (coarse grain) vs. FPGA (fine grain) Status: ~1998 TU Kaiserslautern roughly: performance (MOPS/m. W, orders of magnitude) µProc DSP FPGA r. DPA hardwired © 2004, reiner@hartenstein. de 0 1 2 3 3 roughly: area efficiency (transistors/chip, orders of magnitude) µProc commodity FPGA r. DPA hardwired 40 0 2 4 4 http: //hartenstein. de

TU Kaiserslautern System gates 10 000 Mega-r. GAs per r. GA chip [Xilinx Data] planned Virtex II 1 000 Virtex XC 40250 XV XC 4085 XL 100 000 1 000 500 200 1984 1986 1988 © 2004, reiner@hartenstein. de 1990 1992 1994 41 1996 1998 2000 Jahr 2002 2004 http: //hartenstein. de

TU Kaiserslautern entire system on a single chip • Xilinx Virtex-II Pro FPGA Architecture • Power. PC 405 RISC CPU (PPC 405) cores • FPGA Fabric-based on Virtex-II Architecture all you need on board Rocket IO Power PC Core On Chip Memory Controller Embeded RAM Source: Ivo Bolsens, Xilinx © 2004, reiner@hartenstein. de 42 http: //hartenstein. de

[ST microelectronics] Mask & NRE cost TU Kaiserslautern © 2004, reiner@hartenstein. de 43 http:

>> coarse-grained Platforms << TU Kaiserslautern • Machine vs. Anti Machine • Terminology • Morphware Platforms • coarse-grained Platforms • Dual Machine Paradigms http: //www. uni-kl. de • Final Remarks © 2004, reiner@hartenstein. de 44 http: //hartenstein. de

TU Kaiserslautern y 1 - x 3 y 2 sys Computing in space and time tol this dichotomy is i c completely ignored DP A by our CS curricula y 3 - - a 13 a 23 a 33 - a 12 a 22 a 32 x 1 a 11 a 21 a 31 - - x 2 y 1(0 ) y 2( 0) y 3( 0) © 2004, reiner@hartenstein. de placement computing systolic arrays in space in time etc. data streams flowware 45 migration by re-timing and other transformations http: //hartenstein. de

Flowware programs c i l o t s DPA time | | s“ © 2004, reiner@hartenstein. de time - - x x x - - - x x x port # tr ea m port # - - - x x x - - „d at as input data streams | x x x - | | | x x x time x x x 46 | y s A P D x x x x x | TU Kaiserslautern Flowware defines: . . . which data item time at which port data streams port # output data streams | x x x http: //hartenstein. de

Mathematicians X-ing TU Kaiserslautern Mathematicians like to wax rhapsodic about the elegance, beauty and depth of their proofs. Systolic Synthesis John Horgan: „The End of Science Revisited“ Mathematicians like the beauty and elegance of Systolic Arrays. Due to a lack of depth in understanding, their efforts yielded poor synthesis algorithms. Reiner Hartenstein © 2004, reiner@hartenstein. de 47 http: //hartenstein. de

Generalized Stream-based Computing System heterogenous Array of r. DPUs (reconf. data path units) TU Kaiserslautern c i l o t s y s The same mapper for both: Reconfigurable, or hardwired A P r. D 1 2 3 4 r pe su + + * xf sh sh * - f pip ree e n fo et rm wo rk © 2004, reiner@hartenstein. de y a * + Kress DPSS [1995] DPU architectures x expression tree simultaneous placement & routing Mapper configware data streams 48 Scheduler e c a sp e m i t d e t flowware a l u m g i n s i l a Configware anne Compiler http: //hartenstein. de

Supersystolic Array Principles TU Kaiserslautern • take systolic array principles • replace classical synthesis by simulated annealing • yields the supersystolic array • a generalization of the systolic array • no more restricted to regular data dependencies • now reconfigurability makes sense: use morphware © 2004, reiner@hartenstein. de 49 http: //hartenstein. de

flowware history TU Kaiserslautern time flowware history: 1995: super systolic r. DPA (Kress) 1996+: SCCC (LANL), SCORE, ASPRC, Bee (UCB), . . . | port # - - - x x x time - - x x x - - - - x x x port # | | | x x x 50 input data streams | x x x - (tutorials and courses available on all this) © 2004, reiner@hartenstein. de | time x x x | time DPA | 1980: data streams (Kung, Leiserson) x x x x x port # output data streams | x x x http: //hartenstein. de

computing paradigms and methodologies 1946: machine paradigm (von Neumann) 1980: data streams (Kung, Leiserson) 1989: anti machine paradigm 1990: r. DPU (Rabaey) 1994: anti machine high level programming language 1995: super systolic array (r. DPA) flowware* TU Kaiserslautern sys for tolic dep regu array s: end lar enc dat ies a onl y 1996+: SCCC (LANL), SCORE, ASPRC, Bee (UCB), . . . 1997+: discipline of distributed memory architecture 1997: configware / software partitioning compiler © 2004, reiner@hartenstein. de 51 http: //hartenstein. de

Super Pipe Networks TU Kaiserslautern supersystol ic The key is mapping , rather than

Programming Language Paradigms TU Kaiserslautern ve ry ea sy lea to rn mu ©

Similar Programming Language Paradigms TU Kaiserslautern © 2004, reiner@hartenstein. de very ea sy to

Machine Paradigms TU Kaiserslautern ( “instruction fetch” ) *) e g. Bee project Prof.

r. DPA mapping algorithms efficently onto r. DPA TU Kaiserslautern SNN filter on Kress. Array rout thru only array size: 10 x 16 = 160 r. DPUs d e r tu e c u r war t S „ ig f n Co sign“ [R. H. ] De backbus connect not used by the way: example of scalability / relocatability by EDA support also FPGA scalability (avoid routing congestion) by EDA solution © 2004, reiner@hartenstein. de 56 http: //hartenstein. de

Xplorer Plot: SNN Filter Example TU Kaiserslautern [13] http: //kressarray. de 2 hor. NNports, 32 bit 3 vert. NNports, 32 bit route-thru-only r. DPU © 2004, reiner@hartenstein. de + result operand 57 operator operand route thru backbus connect http: //hartenstein. de

>>> distributed memory TU Kaiserslautern The new discipline of (application-specific) distributed memory [] Herz et al. : proc. IEEE ICECS 2002 © 2004, reiner@hartenstein. de 58 http: //hartenstein. de

TU Kaiserslautern Synthesizable distributed memory architecture. . . for a Stream-based Soft Machine “instructions” r. DPA Compiler Memory Scheduler (data memory) memory bank . . . memory bank Sequencers (data stream generator ) © 2004, reiner@hartenstein. de 59 http: //hartenstein. de

Synthesizable Distributed Memory TU Kaiserslautern An example by Nageldinger’s Kress. Array Xplorer Efficient Memory Communication should be directly supported by the Mapper Tools Legend: Optimized Parallel memory ports Memory Controller sequencers application not used http: //kressarray. de © 2004, reiner@hartenstein. de 60 http: //hartenstein. de

TU Kaiserslautern © 2004, reiner@hartenstein. de Coarse Grain Architectures 61 http: //hartenstein. de

Primarily Mesh-based …. TU Kaiserslautern © 2004, reiner@hartenstein. de 62 http: //hartenstein. de

UC Berkeley (Jan Rabaey) TU Kaiserslautern © 2004, reiner@hartenstein. de 63 http: //hartenstein. de

r. DPA TU Kaiserslautern commercial r. DPA example: PACT XPP - XPU 128 XPP 128 r. DPA r. DPU • Full 32 or 24 Bit Design working silicon • 2 Configuration Hierarchies • Evaluation Board available, and • XDS Development Tool with Simulator © 2004, reiner@hartenstein. de buses not shown © PACT AG, Munich http: //pactcorp. com 64 http: //hartenstein. de

XPP 64 A: Platform Development Board TU Kaiserslautern - SDR Board In Debug Phase -> XPP 64 A Chips from STMicro Fab - Assembly & Test / Available March 2003 © 2004, reiner@hartenstein. de 65 http: //hartenstein. de

PACT Corp TU Kaiserslautern • Xtreme Processor Platform (XPP) family of IP cores, high-speed data -stream-capable, scalable, reconfigurable clusters of arrays of 32 bit DPUs with embedded memories, and high-speed I/O ports • Application development support software featuring a flow graphstyle algorithm mapping language - to minimize training requirements. • XPP's fabrics, featuring automatic Data. Flow synchronization and flagged Event Network to dynamically configure the execution flow, • Supports dynamic RTR: hierarchical configuration managers free the designer from chip-level details and ensure that configurations are independently loaded in exactly the intended order. • Automatic event-based task swapping along with data streams: released resources automatically reconfigured immediately © 2004, reiner@hartenstein. de 66 http: //hartenstein. de

Sequential Processor Model © 2003, PACT AG TU Kaiserslautern Conventional processors use the sequential model: Each operation takes one clock cycle. Multiple operations are computed consecutively. Register Operation 1 Operation 2 Operation 3 Operation 4 Operation 5 Time © 2004, reiner@hartenstein. de 67 http: //hartenstein. de

© 2003, PACT AG A New Parallel Processor Paradigm TU Kaiserslautern Multiple computations are configured as code sections onto a two dimensional array. y Data Buffer x © 2004, reiner@hartenstein. de 68 Time http: //hartenstein. de

Parallel Processor Model © 2003, PACT AG TU Kaiserslautern Multiple code sections are computed sequentially. y Section 1 x Operation 2 Section 3 © 2004, reiner@hartenstein. de Time 69 http: //hartenstein. de

Dataflow Performance © 2003, PACT AG TU Kaiserslautern Traditional Microprocessor XPP Architecture Instruction Memory and cache ALU Configuration Memory and cache Register ADD MULT Array of ALUs One word Filter One operation per cycle FFT SHIFT Basic machine operations performed on single words © 2004, reiner@hartenstein. de Buffer Stream of words Many operations per cycle Viterbi 70 Complex Functions performed on data streams http: //hartenstein. de

instruction stream-based Compilation Principles TU Kaiserslautern 1 -D memory space source text parser library link/load instruction call placement scheduler execution order by location © 2004, reiner@hartenstein. de 71 http: //hartenstein. de

Datastream-based Compilation Principles TU Kaiserslautern library mapper placement & routing scheduler data stream assembly

>> Dual Machine Paradigms << TU Kaiserslautern • Machine vs. Anti Machine • Terminology • Morphware Platforms • coarse-grained Platforms • Dual Machine Paradigms http: //www. uni-kl. de © 2004, reiner@hartenstein. de • Final Remarks 73 http: //hartenstein. de

TU Kaiserslautern 3 rd machine model became mainstream mainframe age compile main frame instructionstream-based computer age (PC age) compile design (Makimtos wave) © 2004, reiner@hartenstein. de e l b ma m a r µProc. accel. prog µProc. r. DPA 1967 1957 morphware age 2007 1987 1977 1997 74 http: //hartenstein. de

benefit from RAM-based & 2 nd paradigm TU Kaiserslautern RAM-based platform needed for: • flexibility, programmability • avoiding the need of specific silicon simple 2 nd machine paradigm needed as a common model: • to avoid the need of circuit expertize • needed to to educate zillions of programmers what programming source language ? © 2004, reiner@hartenstein. de 75 http: //hartenstein. de

Mc. Kinsey Curve: dynamics of R&D disciplines TU Kaiserslautern new discipline on top of it by. . maturity of a discipline saturation: limitations met. . . by innovation consolidation year fundmental issues © 2004, reiner@hartenstein. de 76 http: //hartenstein. de

EDA Industry Revolutions TU Kaiserslautern EDA industry paradigm switching every 7 years courtesy [Keutzer / Newton] 1999 1992 HLLs, (Co-) Compilation Data-Stream-based DPU arrays Synthesis: Cadence, Synopsys. . . 1985 1978 coming closer to programmers ‘ mind set 2006 Schematics entry: Daisy, Mentor, Valid. . . Transistor entry: Applicon, Calma, CV. . . © 2004, reiner@hartenstein. de 77 http: //hartenstein. de

How to achieve acceptance TU Kaiserslautern how to hide the ugliness from the user [Herman Schmit] No hardware description languages [Courtesy Richard Newton] Tools usable by users not being hardware designers Courses tailored for students not being hardware-savvy EDA tools based on term rewriting [Arvind] [Mauricio Ayala] Your name here: your proposals © 2004, reiner@hartenstein. de 78 http: //hartenstein. de

configware compiler TU Kaiserslautern source „program“ configware compiler anti machine © 2004, reiner@hartenstein. de

Configware Compilation memory bank TU Kaiserslautern source „program“ mapper configware compiler data scheduler Placement & routing anti machine e d o c are w g i f n co 80 (r)DPA s m a ed e tr amm e s a gr ar t da pro loww f y b as. M . . . . flowware code © 2004, reiner@hartenstein. de data counter as. M http: //hartenstein. de

TU Kaiserslautern symbiosis of machine models source „program“ software compiler configware compiler µProc. ©

TU Kaiserslautern symbiosis of machine models source „program“ partitioning compiler µProc. r DPA ©

Software / Configware Co-Compilation Juergen Becker’s Co. De-X, 1996 TU Kaiserslautern High level PL source “v. N" machine paradigm Partitioner anti machine paradigm CW SW Analyzer compiler / Profiler compiler SW code © 2004, reiner@hartenstein. de CW Code 83 supporting different platforms Resource Parameters http: //hartenstein. de

Loop Transformation Examples TU Kaiserslautern sequential processes: loop 1 -16 body endloop resource parameter driven Co-Compilation host: loop 1 -8 trigger endloop 1 -8 fork body loop 1 -8 loop 9 -16 endloop body endloop unrolling loop 1 -4 trigger endloop 1 -2 trigger endloop join strip mining © 2004, reiner@hartenstein. de reconf. array: 84 http: //hartenstein. de

>> final remarks << TU Kaiserslautern • Machine vs. Anti Machine • Terminology • Morphware Platforms • coarse-grained Platforms • Dual Machine Paradigms http: //www. uni-kl. de © 2004, reiner@hartenstein. de • Final Remarks 85 http: //hartenstein. de

TU Kaiserslautern http: //ha rtenstein Jürgen Becker . de/Ph-D -Theses. h tml Dissertation Jürgen Becker: Professor at Univ. Karlsruhe • . . . Automatically partitioning Co-compiler • (configware / software co-compilation) • Resource-parameter-driven retargettable • Profiler-driven optimization • Accepts HLL „ALE-X“ (extended C subset) • (subset: pointers not supported) © 2004, reiner@hartenstein. de 86 http: //hartenstein. de

TU Kaiserslautern http: //ha rtenstein . de/Ph-D Rainer Kress -Theses. h tml Dissertation Rainer Kress: infineon technologies, Munich • . . . on mapping applications onto his* Kess. Array • DPSS datapath synthesis system • Including a data scheduler • (data stream scheduler) • Generalization of the Systolic Array • (Kress. Array is a super systolic array) • 32 bit design via Eurochip support © 2004, reiner@hartenstein. de 87 http: //hartenstein. de