Real Processors Lecture for CPSC 5155 Edward Bosworth

Real Processors Lecture for CPSC 5155 Edward Bosworth, Ph. D. Computer Science Department Columbus State University

n n Pipelining: executing multiple instructions in parallel To increase ILP n Deeper pipeline n n Less work per stage shorter clock cycle Multiple issue n n Replicate pipeline stages multiple pipelines Start multiple instructions per clock cycle CPI < 1, so use Instructions Per Cycle (IPC) E. g. , 4 GHz 4 -way multiple-issue n n 16 BIPS, peak CPI = 0. 25, peak IPC = 4 But dependencies reduce this in practice § 4. 10 Parallelism and Advanced Instruction Level Parallelism Instruction-Level Parallelism (ILP) Chapter 4 — The Processor — 2

Multiple Issue n Static multiple issue n n Compiler groups instructions to be issued together Packages them into “issue slots” Compiler detects and avoids hazards Dynamic multiple issue n n n CPU examines instruction stream and chooses instructions to issue each cycle Compiler can help by reordering instructions CPU resolves hazards using advanced techniques at runtime Chapter 4 — The Processor — 3

Speculation n “Guess” what to do with an instruction n n Start operation as soon as possible Check whether guess was right n n If so, complete the operation If not, roll-back and do the right thing Common to static and dynamic multiple issue Examples n Speculate on branch outcome n n Roll back if path taken is different Speculate on load n Roll back if location is updated Chapter 4 — The Processor — 4

Compiler/Hardware Speculation n Compiler can reorder instructions n n n e. g. , move load before branch Can include “fix-up” instructions to recover from incorrect guess Hardware can look ahead for instructions to execute n n Buffer results until it determines they are actually needed Flush buffers on incorrect speculation Chapter 4 — The Processor — 5

The Dynamic–Static Interface • The term “microarchitecture” is used to denote those parts of the hardware not directly accessible through the ISA (Instruction Set Architecture). • The term “dynamic–static interface” was coined in the late 1980’s to emphasize the fact that the ISA of every computer implies an interface between the compiler and the microarchitecture.

Performance and the DSI • Every modern computer is a system with at least three components: hardware, compiler, and the operating system. • The ISA forms a contract between two major layers: the compiler and the hardware. • A good design asks these questions: 1. What optimizations are best handled by the compiler? 2. What performance boosts are best handled by the microarchitecture?

The DSI Defined • The DSI is a dividing line between the tasks and optimizations performed by the compiler (the “static domain”) and the tasks and optimizations performed by the datapath (the “dynamic domain”). The static domain is depicted as “above” the DSI line and the dynamic domain is depicted as “below” the DSI line.

The DSI Line • All features in the ISA are exposed to the software (compiler or assembler) in the static domain and may be manipulated in order to increase efficiency. • All features in the dynamic domain belong to the microarchitecture level, which is the implementation of the ISA. These are hidden from the compiler.

Placing the DSI • The DEL (Direct Executable Language) approach, forgoes the compiler and has the datapath do everything. Sun has a CPU that executes Java.

Placing the DSI • The CISC strategy calls for compilation into a complex assembly language, associated with a complex ISA. There is a lot of complexity for the datapath to handle. The control unit is bigger and slower.

Placing the DSI • The RISC strategy calls for a more sophisticated compiler that emits a simpler assembly language. The datapath is less complex as the compiler handles most of the complexity. The control unit is faster.

Placing the DSI • The VLIW (Very Long Instruction Word) strategy calls for the compiler to group a number of instructions into an issue packet. This is Static Multiple Issue.

Speculation and Exceptions n What if exception occurs on a speculatively executed instruction? n n Static speculation n n e. g. , speculative load before null-pointer check Can add ISA support for deferring exceptions Dynamic speculation n Can buffer exceptions until instruction completion (which may not occur) Chapter 4 — The Processor — 14

Static Multiple Issue n Compiler groups instructions into “issue packets” n n n Group of instructions that can be issued on a single cycle Determined by pipeline resources required Think of an issue packet as a very long instruction n n Specifies multiple concurrent operations Very Long Instruction Word (VLIW) Chapter 4 — The Processor — 15

Scheduling Static Multiple Issue n Compiler must remove some/all hazards n n n Reorder instructions into issue packets No dependencies with a packet Possibly some dependencies between packets n n Varies between ISAs; compiler must know! Pad with nop if necessary Chapter 4 — The Processor — 16

MIPS with Static Dual Issue n Two-issue packets n n n One ALU/branch instruction One load/store instruction 64 -bit aligned n n ALU/branch, then load/store Pad an unused instruction with nop Address Instruction type Pipeline Stages n ALU/branch IF ID EX MEM WB n+4 Load/store IF ID EX MEM WB n+8 ALU/branch IF ID EX MEM WB n + 12 Load/store IF ID EX MEM WB n + 16 ALU/branch IF ID EX MEM WB n + 20 Load/store IF ID EX MEM WB Chapter 4 — The Processor — 17

Hazards in the Dual-Issue MIPS n n More instructions executing in parallel EX data hazard n n Forwarding avoided stalls with single-issue Now can’t use ALU result in load/store in same packet n n n Load-use hazard n n add $t 0, $s 1 load $s 2, 0($t 0) Split into two packets, effectively a stall Still one cycle use latency, but now two instructions More aggressive scheduling required Chapter 4 — The Processor — 18

Scheduling Example n Schedule this for dual-issue MIPS Loop: lw addu sw addi bne Loop: n $t 0, $s 1, 0($s 1) $t 0, $s 2 0($s 1) $s 1, – 4 $zero, Loop # # # $t 0=array element add scalar in $s 2 store result decrement pointer branch $s 1!=0 ALU/branch Load/store cycle nop lw 1 addi $s 1, – 4 nop 2 addu $t 0, $s 2 nop 3 bne sw $s 1, $zero, Loop $t 0, 0($s 1) $t 0, 4($s 1) 4 IPC = 5/4 = 1. 25 (c. f. peak IPC = 2) Chapter 4 — The Processor — 19

Loop Unrolling n Replicate loop body to expose more parallelism n n Reduces loop-control overhead Use different registers per replication n n Called “register renaming” Avoid loop-carried “anti-dependencies” n n Store followed by a load of the same register Aka “name dependence” n Reuse of a register name Chapter 4 — The Processor — 20

Loop Unrolling Example Loop: ALU/branch Load/store cycle addi $s 1, – 16 lw $t 0, 0($s 1) 1 nop lw $t 1, 12($s 1) 2 addu $t 0, $s 2 lw $t 2, 8($s 1) 3 addu $t 1, $s 2 lw $t 3, 4($s 1) 4 addu $t 2, $s 2 sw $t 0, 16($s 1) 5 addu $t 3, $t 4, $s 2 sw $t 1, 12($s 1) 6 nop sw $t 2, 8($s 1) 7 sw $t 3, 4($s 1) 8 bne n $s 1, $zero, Loop IPC = 14/8 = 1. 75 n Closer to 2, but at cost of registers and code size Chapter 4 — The Processor — 21

Dynamic Multiple Issue n n “Superscalar” processors CPU decides whether to issue 0, 1, 2, … each cycle n n Avoiding structural and data hazards Avoids the need for compiler scheduling n n Though it may still help Code semantics ensured by the CPU Chapter 4 — The Processor — 22

Dynamic Pipeline Scheduling n Allow the CPU to execute instructions out of order to avoid stalls n n But commit result to registers in order Example n lw $t 0, 20($s 2) addu $t 1, $t 0, $t 2 sub $s 4, $t 3 slti $t 5, $s 4, 20 Can start sub while addu is waiting for lw Chapter 4 — The Processor — 23

Dynamically Scheduled CPU Preserves dependencies Hold pending operands Results also sent to any waiting reservation stations Reorders buffer for register writes Can supply operands for issued instructions Chapter 4 — The Processor — 24

Register Renaming n n Reservation stations and reorder buffer effectively provide register renaming On instruction issue to reservation station n If operand is available in register file or reorder buffer n n n Copied to reservation station No longer required in the register; can be overwritten If operand is not yet available n n It will be provided to the reservation station by a function unit Register update may not be required Chapter 4 — The Processor — 25

Speculation n Predict branch and continue issuing n n Don’t commit until branch outcome determined Load speculation n Avoid load and cache miss delay n n n Predict the effective address Predict loaded value Load before completing outstanding stores Bypass stored values to load unit Don’t commit load until speculation cleared Chapter 4 — The Processor — 26

Why Do Dynamic Scheduling? n n Why not just let the compiler schedule code? Not all stalls are predicable n n Can’t always schedule around branches n n e. g. , cache misses Branch outcome is dynamically determined Different implementations of an ISA have different latencies and hazards Chapter 4 — The Processor — 27

Does Multiple Issue Work? The BIG Picture n n n Yes, but not as much as we’d like Programs have real dependencies that limit ILP Some dependencies are hard to eliminate n n Some parallelism is hard to expose n n Limited window size during instruction issue Memory delays and limited bandwidth n n e. g. , pointer aliasing Hard to keep pipelines full Speculation can help if done well Chapter 4 — The Processor — 28

Power Efficiency n n Complexity of dynamic scheduling and speculations requires power Multiple simpler cores may be better Microprocessor Year Clock Rate Pipeline Stages Issue width Out-of-order/ Speculation Cores Power i 486 1989 25 MHz 5 1 No 1 5 W Pentium 1993 66 MHz 5 2 No 1 10 W Pentium Pro 1997 200 MHz 10 3 Yes 1 29 W P 4 Willamette 2001 2000 MHz 22 3 Yes 1 75 W P 4 Prescott 2004 3600 MHz 31 3 Yes 1 103 W Core 2006 2930 MHz 14 4 Yes 2 75 W Ultra. Sparc III 2003 1950 MHz 14 4 No 1 90 W Ultra. Sparc T 1 2005 1200 MHz 6 1 No 8 70 W Chapter 4 — The Processor — 29

72 physical registers § 4. 11 Real Stuff: The AMD Opteron X 4 (Barcelona) Pipeline The Opteron X 4 Microarchitecture Chapter 4 — The Processor — 30

The Opteron X 4 Pipeline Flow n For integer operations n n n FP is 5 stages longer Up to 106 RISC-ops in progress Bottlenecks n n n Complex instructions with long dependencies Branch mispredictions Memory access delays Chapter 4 — The Processor — 31

§ 4. 13 Fallacies and Pitfalls Fallacies n Pipelining is easy (!) n n The basic idea is easy The devil is in the details n n e. g. , detecting data hazards Pipelining is independent of technology n n n So why haven’t we always done pipelining? More transistors make more advanced techniques feasible Pipeline-related ISA design needs to take account of technology trends n e. g. , predicated instructions Chapter 4 — The Processor — 32

Pitfalls n Poor ISA design can make pipelining harder n e. g. , complex instruction sets (VAX, IA-32) n n n e. g. , complex addressing modes n n Significant overhead to make pipelining work IA-32 micro-op approach Register update side effects, memory indirection e. g. , delayed branches n Advanced pipelines have long delay slots Chapter 4 — The Processor — 33

n n n ISA influences design of datapath and control Datapath and control influence design of ISA Pipelining improves instruction throughput using parallelism n n § 4. 14 Concluding Remarks More instructions completed per second Latency for each instruction not reduced Hazards: structural, data, control Multiple issue and dynamic scheduling (ILP) n n Dependencies limit achievable parallelism Complexity leads to the power wall Chapter 4 — The Processor — 34