RAVI PAYAL 1 FLIP FLOPS DIGITAL CIRCUITS ELECTRONICS

Out-of-class Activity Design 2 Learning Objective(s) of Out-of-Class Activity: At the end of watching

Out-of-class Activity Design - 2 3 Main Video Source URL https: //youtu. be/r. F_w.

Out-of-class Activity Design - 3 4 Aligning Assessment with Learning Objective Flip. Flop Triggering

Out-of-class Activity Design - 3 5 Aligning Assessment with Learning Objective Assessment Strategy RS

Slides: 5

RAVI PAYAL 1 FLIP FLOPS DIGITAL CIRCUITS ELECTRONICS Btech 2 nd Year Student of Electrical Enggerin CDAC, Noida IDP in Educational Technology, IIT Bombay

Out-of-class Activity Design 2 Learning Objective(s) of Out-of-Class Activity: At the end of watching the videos student should be able to, 1. Understand Flip. Flops 2. Difference between Positive and Negative Edge Triggering of Flip. Flop 3. SR Flip. Flop Working using Nand Nor Gate. Key Concept(s) to be covered: 1. 2. 3. 4. Flip. Flop Triggering of Flip. Flop RS Flip. Flop Using Nand Gate RS Flip. FLop Using Nor Gate IDP inducational Technology, IIT Bombay

Out-of-class Activity Design - 2 3 Main Video Source URL https: //youtu. be/r. F_w. ASn. SZkk Mapping Concept to Video Source CONCEPT Flip. Flop Triggering of Flip. Flop RS Flip. Flop Using Nand Gate RS Flip. FLop Using Nor Gate VIDEO SEGMENT DURATION (in min) V 1 - 0. 00 -2. 01 V 2 - 2. 03 -5. 35 3. 32 V 3 – 5. 37 -11. 52 6. 15 V 4 - 11. 53 -13. 11 1. 58 IDP in Educational Technology, IIT Bombay Total Duration 13. 06

Out-of-class Activity Design - 3 4 Aligning Assessment with Learning Objective Flip. Flop Triggering of Flip. Flop Assessment Strategy Q 1. What is Flip. Flop? How many types of Flip. Flop are there in Digital Circuit? Q 1. Explain the Difference between Positive edge triggered Flip. Flop and Negative Edge Triggered Flip. Flop? Use Diagram also Expected Duration (in min) Additional Instructions (if any) Watch V 1 and then answer Q 1 5 minutes IDP in Educational Technology, IIT Bombay Watch V 2 and then answer Q 1

Out-of-class Activity Design - 3 5 Aligning Assessment with Learning Objective Assessment Strategy RS Flip. Flop Using Nand Gate Q 1. Design RS Flip. FLop using Nand Gate and Explain its Truthtable RS Flip. FLop Using Nor Gate Q 1. Design RS Flip. Flop using Nor Gate and Explain its Truthtable Expected Duration (in min) Additional Instructions (if any) 8 minutes Watch V 3 and then answer Q 1. Watch V 4 and then answer Q 1 8 minutes Total activity duration 26 minutes IDP in Educational Technology, IIT Bombay