RAL ASIC Design RD 53 IP WG Presenter

RAL ASIC Design & RD 53 IP WG Presenter: Mark Prydderch ASIC Design Group Leader Science & Technology Facilities Council Rutherford Appleton Laboratory Harwell Oxford Didcot Oxfordshire OX 11 0 QX United Kingdom

RAL ASIC Design Group Mark Prydderch Davide Braga Lawrence Jones HEXITEC CMS Binary Chips R 3 B 7 x 4 mm, 254 Channels, 256 deep pipeline 10. 8 x 4. 8 mm, 254 Channels, Correlation Logic 256 deep pipeline Stephen Thomas 10. 8 x 4. 8 mm, 128 Channels, Timestamp, 12 b ADC 21. 4 x 20. 1 mm 6400 Pixels Stephen Michelle Quentin Bell Key-Charriere Morrissey 130 & 65 nm Development XFEL LPD Rebecca Coath CDS ADC, STAR & C 2 BA ATLAS ABC 130 & HCC 16 b ADC 10 b DAC Bias & Telemetry 14. 5 x 7. 3 mm, 512 pixels, 1536 x 512 analogue memory 16 x 12 b ADC

Example: CDS ADC Features • • • DC Restoration of the CCD video signal. Fully differential-input preamplifier and CDS. 1 V video signal input range. Fully differential pipelined 16 bit ADC with digital error correction. Operation at up to at least 2 Mpixels/s 10 bit Programmable Offset (+/- 500 m. V). 7 bit Programmable Gain (gain = x 1 to x 3) Input referred system noise 3. 5 adu rms 3 -wire serial interface to program video gain & offset. Triple-voting control Logic to protect against SEUs.

IP participation • Clear ideas on how IP libraries should be developed and managed (see Talk by Stephen Bell). • Interested to hear ideas/thoughts of other groups. • We aim to put this into practice with our own internal development programme in 2014. • Interested in developing the ‘Self Biasing Rail to Rail Amp for Bias distribution’. • Would seek an RD 53 partner for the radiation testing.

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