Radar Processing with COTS Components Jack M West

Radar Processing with COTS Components Jack M. West, Brian F. Veale, Jeffrey T. Muehring, and John K. Antonio Texas Tech University DARPA Contract No. F 30602 -97 -2 -0297 Architecture of Prototype System SAR Processing Flow STAP Flow VME Range Compression PCI Azimuth Processing SPARC Annapolis System PC 120 MB/sec Ra ng e PE PE Data Source . . . PE CN Reconfigurable Subsystem CN . . . Doppler Filtering Weight Computation PC 120 MB/sec Data Transfer CN DSP/GPP Subsystem Data Sink Ra ng e Data Transfer Mercury System Range Compression Doppler Azimuth FFT Size Data Transfer Channel Azimuth Sectioned Convolutions Overlap Kernel Size Section Research Topics VME BACKPLANE • Probabilistic Power Prediction Simulator for Xilinx 4000 -series Parts • RACE Network Simulator Physical View of Prototype System HARD DISK DRIVE SPARC DRAM FORCE SPARC 5 V ANNAPOLIS WILD CHILD CN CN ROUT-T CN CN • Selection of FPGA Word Sizes and Formats • Mapping and Scheduling of STAP Data Communications • Weight Calculation Algorithm Selection and Integration with FPGAbased Inner Product Co-Processor SRAM WILD ONE SRAM DRAM ASIC CN PCI MOTHER BOARD DRAM • Series/Parallel FIR Design for FPGAbased Range Compression CN CN PENTIUM CN CN HARD DISK DRIVE MERCURY RACE MCH 9 U BOARD SRAM WILD ONE SRAM WILDFORCE ANNAPOLIS WILDFORCE RIN-T • CN Configuration for SAR Processing HARD DISK DRIVE PENTIUM DRAM PCI MOTHER BOARD • Minimal Power Configuration of FPGA/DSP/GPP System for STAP and SAR Processing