Queue Manager Yuhua Chen WenJing Tang Applied Research

Queue Manager Yuhua Chen, Wen-Jing Tang Applied Research Lab Washington University 25 September 2020

MSR RAD Block Diagram 2 - Yuhua Chen, Wenjing Tang -April 15, 2002

QMGR Top 3 - Yuhua Chen, Wenjing Tang -April 15, 2002

CARL/QMGR Interface 4 - Yuhua Chen, Wenjing Tang -April 15, 2002

QMGR/OSAR 5 - Yuhua Chen, Wenjing Tang -April 15, 2002

QMGR/CCP Interface 6 - Yuhua Chen, Wenjing Tang -April 15, 2002

QMGR/PSM Interface 7 - Yuhua Chen, Wenjing Tang -April 15, 2002

QMGR Block Diagram CCP Free Pointer Controller DISPATCHER (DCHR) CARL 32 96 Queue Length 96 Controller (QLNC) Line Queue Manager (LNQM) 32 36 48 Queue Header Controller (QHDC) 48 36 Switch Queue Manager (SWQM) SRAM Arbitrator 16 36 36 SRAM 36 32 36 36 36 16 LC PSM 16 SW PSM 8 - Yuhua Chen, Wenjing Tang -April 15, 2002 Output Controller (OUTC) 32 32 OSAR

DCHR Top 9 - Yuhua Chen, Wenjing Tang -April 15, 2002

DCHR (Dispatcher) n n Dispatch packet headers to proper processing blocks Recognize SPC return packets and adjust QID accordingly Keep track of Header Only return packets Process multiple copy packets Single Copy Packet Multi Copy Packet Common Reference 10 - Yuhua Chen, Wenjing Tang -April 15, 2002

SRAM Arbitrator 11 - Yuhua Chen, Wenjing Tang -April 15, 2002

SRAM Arbitrator Functions Manage SRAM bandwidth n Arbitrate among all requesting units n » Free PTR CTRL: 1 cycle, Read/Write » Common Ref: 1 cycle, write only » SWQM enqueue: 2 cycles, write only » SWQM dequeue: 2 cycles, read only » LNQM enqueue: 2 cycles, write only » LNQM dequeue: 2 cycles, read only » OUTC: 1 cycle, Read/Write n zero cycle turn around among different units 12 - Yuhua Chen, Wenjing Tang -April 15, 2002

SRAM Arbitrator Write Timing One-Cycle Write Two-Cycle Write 13 - Yuhua Chen, Wenjing Tang -April 15, 2002

SRAM Arbitrator Read Timing One-Cycle Read Two-Cycle Read 14 - Yuhua Chen, Wenjing Tang -April 15, 2002

Packet Header Format (in SRAM) 15 - Yuhua Chen, Wenjing Tang -April 15, 2002

Queue Manager Artichecture Reserved flows To Output 0 . . . 0 0 … … To SW Port 0 Line Card QMGR To Output 7 … Port 0 To LC Datagram flows Switch QMGR … Port 7 Switch QMGR 16 - Yuhua Chen, Wenjing Tang -April 15, 2002 7 7 Port 7 Line Card QMGR

SWQM Top 17 - Yuhua Chen, Wenjing Tang -April 15, 2002

Per Output Queue Table (SWQM) Output Port # Queue Tail Head 0 1 2 3 4 5 6 7 Output Queue Table 18 - Yuhua Chen, Wenjing Tang -April 15, 2002 External SRAM Packet Headers

LNQM Top 19 - Yuhua Chen, Wenjing Tang -April 15, 2002

Line Card Queue List (LNQM) Queue Headers Packet Headers Current Queue Previous Queue Header Table (on-chip Block RAM) 20 - Yuhua Chen, Wenjing Tang -April 15, 2002 External SRAM

QLNC Top 21 - Yuhua Chen, Wenjing Tang -April 15, 2002

QLENC Functions Keep track of per flow queue length n Respond to queue length inquiry from CCP n Respond to queue length inquiry from LNQM n Packet Drop Policy will be implemented here n 22 - Yuhua Chen, Wenjing Tang -April 15, 2002

Free PTR CTRL Top 23 - Yuhua Chen, Wenjing Tang -April 15, 2002

Free PTR CTRL Functions n Manage External SRAM space » Initialize free pointer list » Maintain free pointer list Handle free pointer fetch & return n Maintain on-chip free pointer cache n » Recycle free pointers locally 24 - Yuhua Chen, Wenjing Tang -April 15, 2002

OUTC Top 25 - Yuhua Chen, Wenjing Tang -April 15, 2002

OUTC Functions Send outgoing packet headers to SW/LC OSAR FIFO n Send drop packets to SW/LC PSM drop FIFO n Process multiple copy packets n » Obtain packet pointer » Update Copy Count 26 - Yuhua Chen, Wenjing Tang -April 15, 2002

QMGR Resource Usage QMGR flops LUTs DCHR 462 345 LCQM 916 1248 SWQM 693 564 fptr_ctrl 271 291 sram_arbritrator 204 274 QHDC 86 61 OUTC 417 478 QLENC 519 216 Total 3568 3477 27 - Yuhua Chen, Wenjing Tang -April 15, 2002