QUESTS SPICE Model YoonJong Lee Sr Manager Device

QUESTS SPICE Model Yoon-Jong Lee Sr. Manager Device Engineering Team

Contents 1. SPICE Model - Quality Assurance - 0. 25 um SPICE Model (aa 2533 C 07. A) - 0. 21 um SPICE Model (aa 1833 C 07. 0) 2. Statistical Modeling 3. Interconnect Capacitance 4. Mixed Signal Characterization 5. TCAD Simulation QUESTS

Anam SPICE Model (Modeling from -55 C to 150 C) BSIM 3 v 3. 1 QUESTS Device sizes for modeling (aa 2533 C 07. A) Short Channel, Narrow Width Effects Non-Uniform Doping Effect Drain Induced Barrier Lowering Mobility Reduction with Gate and Substrate Bias Parasitic Source/Drain Resistance Better Fitting Accuracy at Near. Threshold Region for Analog Simulation

Quality Assurance of SPICE Model QUESTS

0. 25 um SPICE Model (aa 2533 C 07. A) QUESTS NMOS Ids-Vds 11. 98/0. 25 VB=0 V T=27 C PMOS Ids-Vds 11. 98/0. 25 VB=0 V T=27 C NMOS Ids-Vgs 11. 98/0. 25 VD=0. 1 V T=27 C PMOS Ids-Vgs 11. 98/0. 25 VD=-0. 1 V T=27 C

0. 21 um SPICE Model (aa 1833 C 07. 0) QUESTS NMOS Ids-Vds 16. 6/0. 21 VB=0 V T=27 NMOS Ids-Vgs 16. 6/0. 21 VD=0. 1 V T=27 PMOS Ids-Vds 16. 6/0. 21 VB=0 V T=27 PMOS Ids-Vgs 16. 6/0. 21 VB=-0. 1 V T=27

Threshold voltage vs. Gate length NMOS PMOS QUESTS aa 2533 C 07. A w/o Pocket aa 1833 C 07. 0 with Pocket

Temperature Characteristics of IDSAT QUESTS NMOS Vdd=2. 8 V VB=0 V PMOS Vdd=-2. 8 V VB=0 V aa 2533 C 07. A NMOS Vdd=2 V VB=0 V PMOS Vdd=-2 V VB=0 V aa 1833 C 07. 0

Gate Delay Time vs. Supply Voltage (aa 2533 C 07. A) QUESTS

Gate Delay Time vs. Temperature (aa 1833 C 07. 0) NMOS = 0. 5/0. 21 um PMOS = 0. 8/0. 21 um Fanout = 1 QUESTS

Process Parameter Distribution Mean=44. 6 S. Dev. =0. 36 Mean = 43. 5 S. Dev. = 0. 37 Mean = 0. 541 S. Dev. = 0. 022 Mean = -0. 510 S. Dev. = 0. 024 QUESTS

Sigma Contour Plot of 10/0. 21 um Device QUESTS (aa 1833 C 07. 0) 240 FF Idsat. P (u. A/um) 220 2σ SF 200 3σ 180 FS 160 140 420 TT SS 440 460 480 500 Idsat. N (u. A/um) 520 540

Interconnect Capacitance QUESTS

Ring Oscillator with Capacitance Loading Schematic of Test Pattern Metal 2 Line Wp/Lp=10/0. 24 Wn/Ln=5/0. 24 Metal 1 & 3 Plate Unit : [um] QUESTS

Gate Delay Time vs. Supply Voltage QUESTS (aa 2533 C 07. A)

Mixed signal resistors ● aa 2533 C 07. A QUESTS

Mixed signal capacitors ● aa 2533 C 07. A * Target value QUESTS

MOSFET mismatch - aa 2533 C 07. A Mismatch σ＝ A /√(W×L) ( W : Gate width , L : Gate length ) QUESTS

Parasitic pnp bipolar characteristics - aa 2533 C 07. A Emitter size : 1 × 1 [um] QUESTS

TCAD Simulation SIMS Profile Calibration I Channel & Well Profile (Boron) QUESTS

TCAD Simulation SIMS Profile Calibration II MDD Profile (Arsenic) QUESTS

TCAD Simulation SIMS Profile Calibration III S/D Profile (Arsenic & Phosphorous) QUESTS

TCAD Simulation QUESTS Simulated & Measured I-V Characteristics Ids vs. Vgs of 0. 21㎛ NMOS Ids vs. Vds of 0. 21㎛ NMOS