Quartus II Basic Training Copyright 2005 Altera Corporation

Programmable Logic Families n Structured ASIC - Hard. Copy® II, Hard. Copy Stratix n High & Medium Density FPGAs - Stratix II, Stratix, APEX™ II, APEX 20 K, & FLEX 10 K® n Low-Cost FPGAs - Cyclone II & Cyclone n FPGAs with Clock Data Recovery - Stratix II GX n CPLDs - MAX II, MAX 7000 & MAX 3000 n Embedded Processor Solutions - Nios II n Configuration Devices - Serial (EPCS) & Enhanced (EPC) Copyright © 2005 Altera Corporation 2

MAX 7000 A & MAX 3000 A Family Overview 5, 000 10, 000 600 1, 250 2, 500 EPM 7512 AE EPM 7256 AE EPM 7128 AE EPM 7032 AE EPM 3512 A EPM 3256 A MAX 7000 A Useable Gates 600 1, 250 2, 500 Macrocells 32 64 128 256 512 Maximum User I/O Pins 34 66 96 158 208 36 68 100 164 212 t. PD (ns) 4. 5 5. 0 7. 5 4. 5 5. 0 5. 5 7. 5 f. CNT (MHz) 227 222 192 127 116 227 222 192 172 116 t. SU (ns) 2. 9 2. 8 3. 3 5. 2 5. 6 2. 9 2. 8 3. 3 3. 9 5. 6 t. CO 1 (ns) 3. 0 3. 1 3. 4 4. 8 4. 7 3. 0 3. 1 3. 4 3. 5 4. 7 Copyright © 2005 Altera Corporation 3 EPM 3128 A EPM 3064 A EPM 3032 A MAX 3000 A EPM 7064 AE Parameter 5, 000 10, 000

Complete Voltage Portfolio 5. 0 V 3. 3 V 2. 5 V MAX 7000 S MAX 7000 AE MAX 7000 B § Performance § § § Leader Feature Leader Wide Range of Package Offerings Industrial-Grade Offerings § High Performance § Feature Leader § Wide Range of Package Offerings MAX 3000 A § Price Leader § Feature & Package Subset of MAX 7000 AE Copyright © 2005 Altera Corporation 4 § High Performance § Feature Leader § Wide Range of Package Offerings

MAX Device Block Diagram Copyright © 2005 Altera Corporation 5

MAX Macrocell Global Clear Clock Parallel Logic Expanders (from other MCs) 7000 has two Global Clock Programmable Register Bypass Product. Term Select Matrix 36 Programmable Interconnect Signals Shared Logic Expanders 16 Expander Product Terms Copyright © 2005 Altera Corporation 6 PRn D Q VCC Clear Select ENA CLRn Clock/ Enable to PIA Select to I/O Control Block

MAX II: The Lowest-Cost CPLD Ever n New Logic Architecture - 1/2 the Cost 1/10 the Power Consumption 2 X the Performance 4 X the Density Non-Volatile, Instant-On n Supports 3. 3 -, 2. 5 - & 1. 8 -V Supply Voltages n Breakthrough Technology to Expand the Market Copyright © 2005 Altera Corporation 7

Flexible Supply Voltage n On-Chip Voltage Regulator n Accepts 3. 3 -, 2. 5 - & 1. 8 -V Supply Inputs n Internally Converted to 1. 8 -V Core Voltage 1. 8 V 2. 5 V 3. 3 V Convenience of 3. 3 V with the Power & Performance of 1. 8 V Copyright © 2005 Altera Corporation 8

MAX II Device Family Device Typical Logic Elements Macro(LEs) cells User I/O Pins Speed Grades Fastest tpd 1 (ns) User Flash Memory (bits) EPM 240 192 80 3, 4, 5 4. 7 8, 192 EPM 570 440 160 3, 4, 5 5. 5 8, 192 EPM 1270 1, 270 980 212 3, 4, 5 6. 3 8, 192 EPM 2210 2, 210 1, 700 272 3, 4, 5 7. 1 8, 192 Copyright © 2005 Altera Corporation 9

MAX II Packaging & User I/O Pins Device 100 -Pin TQFP 1 144 -Pin TQFP 256 -Pin FBGA 2 324 -Pin FBGA 0. 5 -mm Pitch 1. 0 -mm Pitch 16 x 16 mm 22 x 22 mm 17 x 17 mm 19 x 19 mm EPM 240 80 EPM 570 76 EPM 1270 EPM 2210 Denotes Vertical Migration Notes: 1. TQFP: thin quad flat pack 2. Fine. Line BGA® package (1. 0 -mm pitch) Copyright © 2005 Altera Corporation 10 116 160 116 212 204 272

New Small Packages T 100 0. 5 mm TQFP 16 x 16 mm New Packages Partial M 100 0. 5 mm MBGA 6 x 6 mm n F 256 1. 0 mm FBGA 17 x 17 mm Partial M 256 0. 5 mm MBGA 11 x 11 mm Packages minimize PCB area and optimize easeof-use - Partial arrays allow for 2 layer PCB break out Copyright © 2005 Altera Corporation 11

MAX II Architecture Logic Elements (LEs) Staggered I/O Pads Configuration Flash Memory JTAG &

MAX II Logic Element (LE) sload sclear aload Register Chain addnsub Reg data 1 data 2 data 3 cin 4 -Input LUT data 4 clock ena aclr Row, Column & Direct Link Routing Local Routing LUT Chain Register Chain Copyright © 2005 Altera Corporation 13

User Flash Memory n Feature - Flash Memory Storage Bank - 8, 192 Bits Per Device - Interface to SPI, I 2 C, Parallel, or Proprietary Buses n Applications - Store Revision & Serial Number Data - Store Boot-Up & Configuration Data Copyright © 2005 Altera Corporation 14 Industry First! User Flash Memory Block

MAX & MAX II Comparison Parameter MAX II 0. 3 -um EEPROM 0. 18 -um Flash Product Term Look-Up Table (LUT) 32 to 512 Macrocells 128 to 2210 Macrocells (240 to 2, 210 LEs) Global Row & Column None 8 Kbits 212 272 5. 0 V, 3. 3 V, 2. 5 V 3. 3 V/2. 5 V, 1. 8 V 5. 0 V, 3. 3 V, 2. 5 V, 1. 8 V, 1. 5 V Global Clock Networks 2 per Device 4 per Device Output Enables (OEs) 6 to 10 per Device 1 per I/O Pin None 1 per I/O Pin Process Technology Logic Architecture Density Range Routing Architecture On-Chip Flash Memory Maximum User I/O Pins Supply Voltage I/O Voltages Schmitt Triggers Copyright © 2005 Altera Corporation 15

What is Nios II? n Altera’s Second Generation Soft-Core 32 Bit RISC Microprocessor Debug On-Chip ROM On-Chip RAM FPGA Copyright © 2005 Altera Corporation 16 Avalon Switch Fabric Nios II CPU Cache -- Nios Developed By Altera II Plus Internally All Peripherals Written In HDL -- Can Harvard Architecture Be Targeted For All Altera FPGAs -- Synthesis Royalty-Free Using Quartus II Integrated Synthesis UART GPIO Timer SPI SDRAM Controller

Nios II Processor Architecture n Classic - Pipelined RISC Machine 32 General Purpose Registers 3 Instruction Formats 32 -Bit Instructions 32 -Bit Data Path Flat Register File Separate Instruction and Data Cache (configurable sizes) Tightly-Coupled Memory Options Branch Prediction 32 Prioritized Interrupts On-Chip Hardware (Multiply, Shift, Rotate) Custom Instructions JTAG-Based Hardware Debug Unit Copyright © 2005 Altera Corporation 17

Problem: Reduce Cost, Complexity & Power Flash I/O CPU SDRAM I/O I/O I/O FPGA

Problem: Cost, Complexity & System On. Reduce A Programmable Chip (SOPC) Power Flash FPGA SDRAM CPU is a Critical Function Solution: Replace. Control External Devices Required for. Programmable System-Level Logic Integration with Copyright © 2005 Altera Corporation 19

Licensing n Nios II Delivered As Encrypted Megacore - Licensed Via Feature Line In Existing Quartus II License File - Consistent With General Altera Megacore Delivery Mechanism - Enables Detection Of Nios II In Customer Designs (Talkback) n No Nios II Feature Line (Open. Core Plus Mode) - System Runs If Tethered To Host PC - System Times Out If Disconnected from PC After ~ 1 hr n Nios II Feature Line (Active Subscriber) - Subscription and New Dev Kit Customers Obtain Licenses From www. altera. com - Nios II CPU RTL Remains Encrypted n Nios II Source License - Available Upon Request On Case-By-Case Basis - Included With Purchase Of Nios II ASIC License Copyright © 2005 Altera Corporation 20

Quartus II Basic Training Quartus II Development System Feature Overview Copyright © 2005 Altera

Software & Development Tools n Quartus II - All Stratix, Cyclone & Hardcopy Devices - APEX II, APEX 20 K/E/C, Excalibur, & Mercury Devices - FLEX 10 K/A/E, ACEX 1 K, FLEX 6000 Devices - MAX II, MAX 7000 S/AE/B, MAX 3000 A Devices n Quartus II Web Edition - Free Version - Not All Features & Devices Included l n See www. altera. com for Feature Comparison MAX+PLUS® II - All FLEX, ACEX, & MAX Devices Copyright © 2005 Altera Corporation 22

Quartus II Development System n Fully-Integrated Design Tool - Multiple Design Entry Methods - Logic Synthesis - Place & Route - Simulation - Timing & Power Analysis - Device Programming Copyright © 2005 Altera Corporation

Typical PLD Design Flow Design Entry/RTL Coding Design Specification - Behavioral or Structural Description of Design RTL Simulation - Functional Simulation (Modelsim®, Quartus II) - Verify Logic Model & Data Flow (No Timing Delays) LE M 512 M 4 K I/O Synthesis - Translate Design into Device Specific Primitives - Optimization to Meet Required Area & Performance Constraints - Precision Synthesis, Synplify/Synplify Pro, Design Compiler FPGA, Quartus II Place & Route - Map Primitives to Specific Locations inside Target Technology with Reference to Area & Performance Constraints - Specify Routing Resources to Be Used Copyright © 2005 Altera Corporation 24

Typical PLD Design Flow tclk Timing Analysis - Verify Performance Specifications Were Met - Static Timing Analysis Gate Level Simulation - Timing Simulation - Verify Design Will Work in Target Technology PC Board Simulation & Test - Simulate Board Design - Program & Test Device on Board - Use Signal. Tap II for Debugging Copyright © 2005 Altera Corporation 25

Design Entry Methods n Quartus II Top. Level File - Text Editor l l l AHDL Verilog - Schematic Editor l l Block Diagram File Graphic Design File Top-level design files can be schematic, HDL or 3 rd. Party Netlist File . bdf. gdf . bsf . tdf . vhd . v . edf. edif . v, vlg, . vhdl, vqm Block File Symbol File Text File Text File - Memory Editor l l n HEX MIF Generated within Quartus II 3 rd-Party EDA Tools - EDIF - HDL - VQM n Mixing & Matching Design Files Allowed Copyright © 2005 Altera Corporation 26 Imported from 3 rd-Party EDA tools

Quartus II Basic Training Quartus II Quick Start LAB 1 Copyright © 2005 Altera

Objectives n Create a project using the New Project Wizard n Name the project

Step 1 (Setup Project for QII 5_1) Under File, Select New Project Wizard…. A

Step 2 (Setup Project for QII 5_1) Page 1 of the wizard should be completed with the following working directory for this project <lab_install_directory> Dsp_7_segment name of project Dsp_7_segment top-level design entity Dsp_7_segment Copy “state_machine. v” and past in Dsp_7_segment Click Next to advance to the Project Wizard: Add Files [page 2 of 5]. Copyright © 2005 Altera Corporation 30

Step 3 (Setup Project for QII 5_1) Using the browse button, select state_machine. v

Step 4 (Setup Project for QII 5_1) On page 3, select Stratix as the Family. Also, in the Filters section, set Package to FBFA, Pin count to 780, and Speed grade to 5. Select the EP 1 S 25 F 780 C 5 device from the Available devices: window. Click Next. Copyright © 2005 Altera Corporation 32

Step 5 (Setup Project for QII 5_1) On page 4 , you can specify any third party EDA tools you may be using along with Quartus II. Since these exercises will be done entirely within Quartus II, click Next. Copyright © 2005 Altera Corporation 33

Step 6 (Setup Project for QII 5_1) The summary screen appears as shown. Click

Quartus II Basic Training Quartus II Quick Start LAB 2 Copyright © 2005 Altera

Objectives n Create a counter using the Mega. Wizard Plug-in Manager n Build a design using the schematic editor n Analyze and elaborate the design to check for errors Copyright © 2005 Altera Corporation 36

Step 1 Create schematic file Select File New and select Block Diagram/Schematic File. Click OK. Select File Save As and save the file as <lab_install_directory> Dsp_7_segment Dsp_7_segment. bdf Copyright © 2005 Altera Corporation 37

Step 2 Build an 23 bits counter using the Mega. Wizard Plug-in Manager 1. Choose Tools Mega. Wizard Plug-In Manager. In the window that appears, select Create a new custom megafunction variation. Click on Next. 2. On page 2 a of the Mega. Wizard expand the arithmetic folder and select LPM_COUNTER. 3. Choose Verilog HDL output For the name of the output file, type timer_1 s. Click on Next Copyright © 2005 Altera Corporation 38

Step 3 1. 2. 3. Set the output bus to 27 bits. For the remaining settings in this window, use the defaults that appear. . Select next. Turn on “Modulus , with a count modulus of “and key in 79999999 Select finish Copyright © 2005 Altera Corporation 39

Step 4 In the Graphic Editor, double-click in the screen so that the Symbol Window appears. Inside the symbol window, click on to expand the symbols defined in the Project folder. Double-click on timer_1 s. Click the left mouse button to put down the symbol inside the schematic file. . The symbol for “timer_1 s” now appears in the schematic. Copyright © 2005 Altera Corporation 40

Step 5 1. 2. 3. 4. From the File menu, open the file state_machine. v From the File menu, go the Create/Update menu option and select Create Symbol Files for Current File. Click Yes to save changes to Dsp_7_segment. bdf. Once Quartus II is finished creating the symbol, click OK. Close the state_machine. v file In the Graphic Editor, double-click in the screen so that the Symbol Window appears again. Double-click on state_machine in the Project folder. Click OK. . . The symbol for state_machine now appears in the schematic. Copyright © 2005 Altera Corporation 41

Step 6 Add Pins to the Design Input Output sys_clk 7_out[6. . 0] reset Dig 1 1. 2. 3. 4. . For each of the pins listed in left Table , you must insert a pin and change its name To place pins in the schematic file, go to Edit Insert Symbol OR double-click in any empty location of the Graphic Editor. Browse to libraries primitives pin folder. Double-click on input or output Hint: To insert multiple pins select Repeat Insert Mode. To rename the pins double-click on the pin name after it has been inserted. Type the name in the Pin name(s) field and Click OK Copyright © 2005 Altera Corporation 42

Step 7 Connect the Pins and Blocks in the Schematic 1. In the left hand tool bar click on button to draw a wire and button to draw a bus. Another way to draw wires and busses is to place the cursor next to the port of any symbol. When you do this, the wire or bus tool will automatically appear. 2. Connect all of the pins and blocks as shown in the figure below Copyright © 2005 Altera Corporation 43

Step 8 Save and check the schematic 1. 2. 3. Click on the Save button in the toolbar to save the schematic. From the Project menu, select Add/Remove Files in Project. Click on the browse button to make sure the Dsp_7_segment. bdf, timer_1 s and state_machine are added to the project. From the Processing menu, select Start Analysis & Elaboration. 4. Analysis and elaboration checks that all the design files are present and connections have been made correctly. Click OK when analysis and elaboration is completed Copyright © 2005 Altera Corporation 44

Quartus II Basic Training Quartus II Quick Start LAB 3 Copyright © 2005 Altera

Objectives n Pin assignment n Perform full compilation Build a design using the schematic

Step 1 1. 2. 3. Choose Assignments Assignment editor. From the View menu, select

Step 2 1. 2. 3. 4. 5. 6. 7. Pls install DSP Development Kit Stratix edtion CD Open ds_stratix_dsp_bd. pdf from C: megacorestratix_dsp_kit-v 1. 1. 0Doc Check clk , pushbotton and seven segment display pin location from ds_stratix_dsp_bd. pdf Key your pin number in location Click on the Save button in the toolbar From Assignments, select Device. Click Device & Pin options. Click Unused pins. Select As input tri-stated from Reserve all unused pins From the Processing menu, select Start Compilation Copyright © 2005 Altera Corporation 48

Step 3 1. 2. 3. 4. From the Tools menu, select programmer Click on Add File. Select Dsp_7_segment. sof. Check Hardware Setup. Select your download cable on Currently selected hardware(Byte. Blaster. II) Select JTAG from Mode Copyright © 2005 Altera Corporation 49

Step 4 1. 2. 3. Turn on Program/configure. Or see figure below Click Start

Signal. Tap II Agenda Signal. Tap II Overview & Features n Using Signal. Tap

Signal. Tap II ELA Captures the Logic State of FPGA Internal Signals Using a Defined Clock Signal n Gives Designers Ability to Monitor Buried Signals n Connects to Quartus II through FPGA JTAG Pins n Captures Real-Time Data n - Up to 200 Mhz n Is Available for Free - Installed with Full Subscription or Web Edition - Installed with Stand-Alone Programmer Copyright © 2005 Altera Corporation 52

Signal. Tap II Device Support n Stratix & Stratix II n Stratix GX n

How Does It Work? 1. Configure ELA 2. Download ELA into FPGA along with

Stratix/Cyclone Sample Resource Usage Number of Channels Logic Elements Trigger Level 1 Trigger Level 2 Trigger Level 3 8 316 371 426 32 566 773 981 256 2900 4528 6156 Number of Channels M 4 Ks Based on Sample Depth 256 512 2 K 8 K 32 K 8 <1 1 4 16 64 32 2 4 16 64 256 16 32 128 512 Copyright © 2005 Altera Corporation 55

Modes of Operation n Three Different Configurations - Internal RAM ELA Configuration - Debug Port ELA Configuration - Hybrid Approach n Provides Flexibility Based on Available Device Resources - Memory Resources Are Limited l Use Debug Port Configuration - Pin Resources Are Limited l Use Internal RAM Configuration Copyright © 2005 Altera Corporation 56

Supported Download Cables n USB Blaster - USB Port Cable n Byte. Blaster™ II - Parallel Port Cable n Byte. Blaster. MV™ - Parallel Port n Master. Blaster™ - USB / Serial Port Cable Copyright © 2005 Altera Corporation 57

Signal. Tap II Key Features n Setup n Data Triggering n Data Capture n

Setup Features Up to 1024 Data Channels n Multiple Analyzers in One Device n - Supports Analysis of Multiple Clock Domains - Each Analyzer Can Run Simultaneously Setup Data Triggering Data Capture Resource Usage Estimation n Incremental Design Support n Copyright © 2005 Altera Corporation 59 Data Analysis

Data Triggering Features n Up to 10 Trigger Levels Per Channel Setup - Allows Application of Simple (Basic) & Complex (Advanced) Triggering Schemes l Defines a Sequential Pattern of Logic Conditions Data Triggering - Each Trigger Level is Logically ANDED l If (L 1 & L 2. . . & L 10) == TRUE Data Capture Data Analysis Copyright © 2005 Altera Corporation 60

Data Triggering Features (Cont. ) n Three Main Trigger Positions Setup trigger Samples Captured Old Samples New Samples TIME n Trigger Input - Setup External Trigger to Trigger the Analyzer n Trigger Output n Use One ELA’s Trigger Output as Trigger Input for Another Data Capture - Signifies Trigger Event Occurred with Signal. Tap II Copyright © 2005 Altera Corporation 61 Data Triggering Data Analysis

Data Capture Features n Up to 128 K Samples Per Channel Setup - Increases Chance of Catching Target Event n Two Methods of Data Acquisition 1. Circular 2. Segmented n Data Capture Mnemonic Tables - Create User-Defined Labels for Bit Sequences (Ex. State Machine) Copyright © 2005 Altera Corporation 62 Data Triggering Data Analysis

Signal. Tap II Design Flow 1) Use Signal. Tap II File (. STP) n Use Quartus II GUI n STP Separate from Design Files 2) Use Quartus II Mega. Wizard n Instantiate Directly into HDL Copyright © 2005 Altera Corporation 63

Using STP File Create. STP File 1. • • • Assign Sample Clock Specify Sample Depth Assign Signals to STP File Specify Triggering Setup JTAG Save. STP File & Compile with Design 3. Program Device 4. Acquire Data 2. Copyright © 2005 Altera Corporation 64

1) Creating a New. STP File n To Create a. STP File - Method 1 l Select the in Quartus II - Method 2 l l l n Select New (File Menu) Other Files Signal. Tap II File Default File Name Will Be STP 1. stp Copyright © 2005 Altera Corporation 65

Main. STP File Components. STP File Instance Manager Waveform Viewer Copyright © 2005 Altera

Instance Manager n Instance Manager - Selects Current ELA to Setup/View - Displays the

Assign Sample Clock Use Global Clock for Best Results n Data Written to Memory on Every Sample Clock Rising Edge n Clock Signal Cannot Be Monitored as Data n External Clock Pin Created Automatically if Clock Unassigned n - auto_stp_external_clock - ELA Expects External Signal to be Connected to Clock Pin Copyright © 2005 Altera Corporation 68

Specify Sample Depth n Sample Depth - Set Number of Samples Stored for each Data Signal - 0 to 128 K Sample Depth l n 0 Selected When External Analyzer Is Used Select RAM Type for Stratix & Stratix II Devices - Useful when Preserving a Specific Memory Type is Necessary Copyright © 2005 Altera Corporation 69

Data Capture n Circular - Specify Trigger Position l l n Pre Center Post

Triggering n Trigger Levels - Indicate up to 10 Trigger Conditions n Trigger-In - Any I/O Pin Can Trigger the Signal. Tap II Analyzer - Generates auto_stp_trigger_in_n Pin n Trigger-Out - Indicates When a Trigger Pattern Occurs - Generates auto_stp_trigger_out_n Pin l Delayed 4 Clock Cycles after Actual Trigger Event Copyright © 2005 Altera Corporation 71

Waveform Viewer n Setup Tab Describes the Signal Settings - Data Signals vs. Trigger Signals - Sets up Each Triggering Level (L 1 – L 10) n Data Tab Displays Captured Data Copyright © 2005 Altera Corporation 72

STP File Waveform Viewer Setup Tab Data Tab Copyright © 2005 Altera Corporation 73

Basic Triggering All Signals Must Be True for Level to Cause Data Capture Right-Click

Debug Port Routes Data Signals to Spare I/O Pins for Capture by External Logic Analyzer n Quartus II Automatically Generates auto_stp_debug_out_m_n Pin n - m Represents the Instance Number of the Analyzer - n Represents the Order the Debug Port Pin Occurs in the Signal List Copyright © 2005 Altera Corporation 75

Mnemonic Table n Allows a Set of Bit Patterns to Be Assigned User. Defined Names - Right-Click in the Setup View of an STP File & Select Mnemonic Setup - Select Add Table - Select Add Entry n Ex. State Machines or Decoders/Encoders Copyright © 2005 Altera Corporation 76

JTAG Chain Configuration n Select Programming Hardware n Scan Chan Button Automatically Determines Devices Physically Connected to the Chain l Detects Non-Altera Devices & Displays Them as Unknown Copyright © 2005 Altera Corporation 77

2) Save. STP File & Compile n Signal. Tap II Logic Analyzer Control in

3) Program Device(s) n Use Quartus II Programmer or STP File - Program Button in the Signal. Tap II Interface Only Configures the Selected Device in Chain - Use Quartus II Programmer to Program Multiple Devices l Can Create a STP File for each Device in the JTAG Chain Copyright © 2005 Altera Corporation 79

4) Acquire Data n Signal. Tap II Toolbar & STP File Controls - Run

Displaying Acquired Data Format in Time or Sample Number Display Signal as Bar or Line Chart n Export to Other Tools for Viewing or Analysis (File Menu) n - Creates. VWF, . TBL, . CSV, . VCD, . JPG or. BMP File Copyright © 2005 Altera Corporation 81

Using STP File Review Create. STP File 1. • • • Assign Sample Clock Specify Sample Depth Assign Signals to STP File Specify Triggering Setup JTAG Save. STP File & Compile with Design 3. Program Device 4. Acquire Data 2. Copyright © 2005 Altera Corporation 82

Recompilation n Recompilation Required - Addition/Removal of Instance, Data or Trigger - Modifying the Sample Clock or Buffer Depth - Enabling/Modifying Trigger-In/Trigger-Out - Enabling the Debug Port n Lock Mode Prevents Changes Requiring Recompilation Copyright © 2005 Altera Corporation 83

Reducing Recompilation Times n Incremental Compilation - Maintains Design Synthesis & Placement - Recompiles Only Logic Analyzer l n Change Signal. Tap II Configuration without Affecting Existing Logic Incremental Routing - Allows Switching Trigger & Data Nodes without Full Recompilation n Cannot Be Used Together in 5. 0 - Use Incremental Compilation First, Switch to Routing - Will Be Supported in Future Version of Quartus II Copyright © 2005 Altera Corporation 84

Signal. Tap II Incremental Compilation 1) Enable Full Incremental Compilation n 2) Any User-Defined Partitions Must Be Removed (5. 0 Limitation) Set Netlist Type of Top-Level Partition to Post-Fit Copyright © 2005 Altera Corporation 85 Assignments Menu

Signal. Tap II Incremental Compilation 3) 4) Compile Design Enable Signal. Tap II Incremental Compilation n n Only Post Fitting Nodes Can Be Incrementally Compiled Quartus II Will Automatically Convert Pre-Synthesis Nodes to Post-Fitting Copyright © 2005 Altera Corporation 86

Signal. Tap II Incremental Routing 1) Enable Smart Recompilation 2) Manually Set the Number of Allocated Nodes - Nodes Acts as Place Holders for Real Signals that Can Be Added Later Auto Creates Enough Nodes for Current Number of Data/Triggers Copyright © 2005 Altera Corporation 87

Signal. Tap II Incremental Routing Add Post-Fitting nodes to STP file 3) - Signal. Tap II: Post-Fitting Nodes Always Incrementally Routed Signal. Tap II: Pre-Synthesis Nodes Always Cause Full Recompilation if Added Later l Benefit of Enabling Incremental Routing on Pre-Synthesis Nodes is They Can Be Removed & Replaced with Post-fitting Nodes without Total Recompilation Pre-Synthesis Nodes Post-fitting Nodes Copyright © 2005 Altera Corporation 88

Quartus II Netlist Optimization n New Synthesis Optimization Features Do Not Work Well with Signal. Tap II - Signal. Tap II Nodes may Disappear - Register Re-timing & WYSIWYG Re-Synthesis Should be Disabled if Signal. Tap II is Used n Set Netlist Optimizations Logic Option to Never Allow on Entities which Have Signal. Tap II Nodes Copyright © 2005 Altera Corporation 89

Performance Preservation n Signal. Tap II can Potentially Effect the Performance of a Design - Routing and/or Placement Can Change n Possible Solution - Back-Annotate Design before Adding Signal. Tap II - See Quartus II Handbook, Volume 3, Chapter 10 for More Suggestions Copyright © 2005 Altera Corporation 90