Pulsar Design Mircea Bogdan Level 2 Pulsar Production

Pulsar Design Mircea Bogdan Level 2 Pulsar - Production Readiness Review Friday, Nov. 7, 2003 1

Level 2 Pulsar – Hardware Requirements • • • Double width, 9 U VME board inside L 2 crate; All the data interfaces that L 2 decision crate has; Data source for all trigger inputs; Can record, reformat and retransmit data from upstream. Can use S-LINK Mezzanine Cards for communication to remote PC. 2

Level 2 Pulsar - Design Issues Parts: Factors considered: Price, existence of simulation models, functionality; - FPGA for VME: EPM 7128 SOC 160 -7 - reuse from CDF Projects - $37. - FPGAs for Data I/O and Control: EP 20 K 400 BC 652 -1 XV - $1, 000. uses +3. 3 V for I/O, +5 V tolerant, hand assigned pins, - FIFO 4 Kx 18 : CY 7 C 4245 -10 ASC – reuse from SVT Projects - $8. 40; - SRAM 128 Kx 36: CY 7 C 1350 -100 AC - $40. 45. POWER: - we estimated +5 V/13 A; - uses (+5 V): 2. 7 A with no MC, 3. 7 A with 1 MC and ~7 A with 4 MC; - generates: +2. 5 V/3 A Max with LM 1085 IT-Adj. ; - generates: +3. 3 V/15 A Max with DATEL UNR-3. 3/20 DC/DC; Configuration Options: - each FPGA has it’s own JTAG Chain with 3 x. EPC 2 LC 20 and 10 pin connector inside board; - one big chain with all 3 x. FPGAs and 9 x. EPC 2 s and 10 pin front panel connector. 3

Level 2 Pulsar – Mezzanine Cards • • The board accepts 4 Mezzanine Cards, 2 for each Data I/O chip. Each Mezzanine Card connected with Data(45: 0) Bus and Ctrl(32: 0) Bus that go directly to the FPGA; Connections are bi-directional for flexibility; CARD_ID(3: 0) for identity check at power-up; prevents signal contention by keeping the I/Os in High Z; Each MC is provided with +5 V, +3. 3 V and +2. 5 V; Design compatible with the Common Mezzanine Card Family Standard (CMC); Two 64 -pin surface-mount CMC connectors; Mezzanine Cards: - Hotlink I/O 4 x. Cypress. Rx/Tx or 2 x. Rx/Tx + lvds - tested; - Taxi I/O 4 x. AMD AM 7968/9 -175 JC TAXI chips –tested; - ODIN S-LINK interface – commercially available 32 -bit data with/40 MHz. CLK/160 MBytes/s max transfer rate; 4

Level 2 Pulsar – Aux Card 9 U VME Aux Card P 3 connections: 2 x S-Link I/O[45: 0] + 1 x Spare Bus[24: 0] FP connections: - 2 x 52 pin SVT/XTRP I/O Connectors; - 2 x 68 pin TS I/O Connectors; - 2 x S-Link Card Connectors. Power options: • 5 V Aux card ~2 A max (0. 9 A with 1 SLINK) • 3. 3 V Aux card ~2 A(5 V) max(0. 7 A with 1 SLINK) The card generates +3. 3 V from +5 V, using UNR-3. 3/15 -D 5. 5

Level 2 Pulsar - Board Specifications 6

Level 2 Pulsar - Trace Analysis We performed signal integrity test on some 80 nets on the board using the Interconnect Synthesis Tool by Mentor Graphics. Most of the IBIS (I/O Buffer Information Specification) models are vendor supplied. For the FPGAs we used Quartus. II generated IBIS models. With no termination With 33 Ohm Series Termination on the Source. 7

Level 2 Pulsar – Multi Board signal integrity We performed signal integrity tests for some nets on the Pulsar Board together with Hot. Link Rx and Tx mezzanine cards using the IS_Multi Board tool by Mentor Graphics. For the 1 mm FH Mezzanine (IEEE 1386), BTB, Surface Mount connectors we used vendor supplied Lumped Constant Model. 8

Level 2 Pulsar – Crosstalk For this board's stackup and considering 1 ns rising edge, we have -21. 02 d. B calculated cross talk coefficient on micro strip traces running 10 mils apart for 4 inches and -18. 81 d. B on stripline traces. We performed cross talk tests for some nets on the board, using the Interconnect Synthesis tool by Mentor Graphics. 9

Level 2 Pulsar - Functional Simulation • Multi-board simulation: -instantiate Pulsar along with MCs in a top level schematic with DA; -run QSII with all the boards working together: 4 x. Tx Hot. Link + 4 x. Rx Hot. Link + Pulsar. 10

Level 2 Pulsar - Layout Top 11

Level 2 Pulsar - Layout Award 12

Level 2 Pulsar – Status –Nov. 7, 2003 • We tested the two “First Item” boards from Promex; • Will make 8 more boards in this production batch; For new production batches with more that 20 boards we estimate: $150/board – Assembly; $1, 300/board – Parts(No Altera) + PCB; $3, 250/board – Altera parts. ----------~$4, 700/board - Total - All the required documents are on the web: http: //fozzie. uchicago. edu/~bogdan/pulsar/index. html 13