PseudoRandom Pattern Generator Design for ColumnMatching BIST Petr

Pseudo-Random Pattern Generator Design for Column‑Matching BIST Petr Fišer Czech Technical University Dept. of Computer Science and Engineering

Outline Introduction Mixed-Mode Column-Matching BIST Weighted-Pattern testing & splitter Results Conclusions

Introduction Discussion on the choice of the pseudorandom pattern generator (PRPG) in connection with Column-Matching BIST design method Target: low area overhead of both the PRPG and other BIST logic

Column-Matching BIST Pseudorandom patterns are generated by PRPG and then modified by a combinational logic into deterministic ones (by output decoder) For test-per-clock, patterns are applied in parallel

Standard Mixed-Mode Column-Matching BIST Combination of pseudorandom and deterministic testing (like bitfixing, bit-flipping). Difference: these phases are disjoint The pseudorandom phase is run first, and then deterministic test is generated for undetected faults 100% fault coverage assumed

PRPG Issues & Choices LFSR CA Sometimes better, but not much (see DSD’ 05) LFSR width is one problem to solve PRPG fault coverage is the second problem

PRPG Issues & Choices m-bit wide LFSR is needed, in the standard approach Usually, m goes to thousands => high PRPG area overhead

Solution 1 Weighted pattern testing (LFSR outputs are AND-ed or OR-ed, to obtain weighted outputs) + Shorter LFSR + Higher fault coverage - Weighting logic overhead

Solution 2 Splitter (LFSR outputs are distributed to m CUT inputs by branching them) + Shorter LFSR - Less fault coverage + No weighting logic overhead

One Remark to This Weighted Pattern Testing 100% fault coverage is not the aim here The aim is minimum area overhead More sophisticated methods, like multiple weights, MPLFSR, GURT, etc. , are not welcome here

Weighting Logic Effects

How to Compute Weights are derived from test vectors detecting random pattern resistant faults (RPRFs) Question: How to find them? Several pseudorandom vectors are applied to the CUT (by fault simulation), undetected faults are RPRFs. Major question: How many vectors?

How to Compute Weights

Some Comparisons c 2670 ISCAS benchmark circuit 233 inputs LFSR (r) method w CM time [s] GEs 233 standard - 219 606 1153. 5 233 3 -w 216 264. 5 960 1415 233 5 -w 406 226 171 1566. 5 50 splitter - 323 475 677. 5 50 3 -w 219 248. 5 427 629. 5

Scaling Down the LFSR size s 13207. 1 ISCAS benchmark circuit 700 inputs LFSR (r) method 700 standard 700 3 -w 200 3 -w w 518 365 CM 172. 5 40. 5 63. 5 time [s] GEs 4720 2975 245 3361 653 1231 50 45 40 30 365 365 103. 5 145. 5 640. 5 - 2835 3423 29434 - 3 -w 3 -w 671 693 1288 -

Conclusions Two (simple) PRPG design methods have been investigated: weighted pattern testing and splitting the LFSR outputs Primarily targeted to lower the area overhead Seems to be simple, but…

Here are the Buts… Weighted pattern testing works well. OK. But how many vectors should be simulated to obtain RPRFs to compute the weights? Numerous experiments have been performed, every benchmark circuit behaves differently

Here are the Buts… How many weights then? No weights, no weighting logic. More decoder logics. Too much weights, too much weighting logics. Less Decoder logics. Numerous experiments have been performed. No clue, unless the final result is computed

Here are the Buts… The LFSR width can be scaled. OK. But to what extent? Numerous experiments have been performed. No clue, unless the final result is computed

One Last Conclusion Lots to think about…