PROGRAMMABLE PERIPHERAL INTERFACE PPI 8255 8255 is a
PROGRAMMABLE PERIPHERAL INTERFACE (PPI) -8255
• 8255 is a general purpose programmable device used for data transfer between processor and I/O devices. • It has 3 programmable I/O ports (PA, PB &PC) and port operation (IN/OUT Port) is defined by control word in the control word register. • Ports are operated in two modes: • i) I/O modes: Mode 0, Mode 1, & Mode 2 • Ii) BSR (Bit set/Reset) mode
About 8255 • PPI has 40 pins and it has three distinct modes of operation. • • Port A (PA 7 -PA 0) : 8 pins • • Port B (PB 7 -PB 0) : 8 pins • • Port C (Pc: Upper: PC 7 -PC 4) : 4 pins • Port C (Pc: Lower: PC 3 -PC)) : 4 pins • Data Bus (D 7 -D 0) : 8 pins • Control signals : 6 pins • VCC and Gnd : 2 pins
Pin Diagram
Pin names and function
8255 Block Diagram
Group A and Group B control: • Group A and B get the Control Signal from CPU and send the command to the individual control blocks. • Group A send the control signal to port A and Port C (Upper) PC 7 -PC 4. • Group B send the control signal to port B and Port C (Lower) PC 3 -PC 0.
FOR I/O MODE: • The control word mode format for I/O as shown in figure
operation modes: i) I/O modes (M 0, M 1, &M 2) ii) BSR (Bit set/Reset) mode
Mode 1: Handshake interrupt i/p port
82 C 55: Mode 1 Strobed Input
Handshake interrupt o/p port • When o/p device wants to receive data it checks if OBF* (output buffer full) signal is 0. • If 0, it receives data on PB 7 -0 and activates ACK* (Acknowledge) signal. ACK* is active low. • When ACK* goes high, the data goes out of the port and OBF* is set to 1. • If the Port interrupt is enabled, INT is activated. This interrupts the processor. • Processor sends another byte to the port during the ISS. Then OBF* and INT are reset to 0.
Mode 1 o/p mode
82 C 55: Mode 2 Bi-directional Operation:
82 C 55: Mode 2 Bi-directional Operation • INTR : Interrupt request is an output that requests an interrupt. • • ~OBF : Output Buffer Full is an output indicating that output buffer contains data for the bi-directional bus. • • ~ACK : Acknowledge is an input that enables tri-state buffers which are otherwise in their high-impedance state. • • ~STB : The strobe input loads data into the port A latch.
82 C 55: Mode 2 Bi-directional Operation • IBF : Input buffer full is an output indicating that the input latch contains information for the external bidirectional bus. • INTE : Interrupt enable are internal bits that enable the INTR pin. BIT PC 6(INTE 1) and PC 4(INTE 2). • PC 2, PC 1, PC 0 : These port C pins are general-purpose I/O pins that are available for any purpose.
FOR BIT SET/RESET MODE (Port C only) • This is bit set/reset control word format.
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