Programmable Logic System Design Lab 07 Hierarchy and

Programmable Logic System Design Lab 07 - Hierarchy and Register SOC LAB. Che-Yuan Sung 2019. 11

Practice 1. N-bit adder using hierarchical package 2. N-bit register 3. 4 -bit shift register 4. Marquee (跑馬燈)

Practice 1：N-bit adder using hierarchical package --(fulladd. vhd) LIBRARY ieee; USE ieee. std_logic_1164. all; ENTITY fulladd IS PORT( Cin, x, y: IN STD_LOGIC; S, Cout : OUT STD_LOGIC); END fulladd; ARCHITECTURE Logic. Func OF fulladd IS BEGIN s <= x XOR y XOR Cin; Cout <= (x AND y) OR (Cin AND x) OR (Cin AND y); END Logic. Func;

Practice 1： N-bit adder using hierarchical package(conti. ) --(fulladd_package. vhd) VHDL Package LIBRARY ieee; USE ieee. std_logic_1164. all; PACKAGE fulladd_package IS COMPONENT fulladd PORT( Cin, x, y: IN STD_LOGIC; S, Cout : OUT STD_LOGIC); END COMPONENT; END fulladd_package;

Practice 1： N-bit adder using hierarchical package(conti. ) --(addern. vhd) LIBRARY ieee; USE ieee. std_logic_1164. all; USE work. fulladd_package. all; -- Using package syntax ENTITY addern IS GENERIC(n: INTEGER: =16); PORT( Cin : IN STD_LOGIC; A, B : IN STD_LOGIC_VECTOR(n-1 DOWNTO 0); Sum : OUT STD_LOGIC_VECTOR(n-1 DOWNTO 0); Cout: OUT STD_LOGIC); END addern; ARCHITECTURE Structure OF addern IS SIGNAL C: STD_LOGIC_VECTOR(1 TO n-1); BEGIN FA_0 : fulladd PORT MAP(Cin, A(0), B(0), Sum(0), C(1)); G_1 : FOR i IN 1 TO n-2 GENERATE FA_I : fulladd PORT MAP(C(i), A(i), B(i), Sum(i), C(i+1)); END GENERATE; FA_n: fulladd PORT MAP (C(n-1), A(n-1), B(n-1), Sum(n-1), Cout); END Structure;

Practice 2：N-bit register -(regn. vhd) LIBRARY ieee; USE ieee. std_logic_1164. all; ENTITY regn IS GENERIC(n: INTEGER: =16); PORT( D : IN STD_LOGIC_VECTOR(n-1 DOWNTO 0); Resetn, Clock : IN STD_LOGIC; Q: OUT STD_LOGIC_VECTOR(n-1 DOWNTO 0)); END regn; ARCHITECTURE Behavior OF regn IS BEGIN PROCESS(Resetn, Clock) BEGIN IF Resetn='0'THEN Q<=(OTHERS=>'0'); ELSIF Clock'EVENT AND Clock='1' THEN Q<=D; END IF; END PROCESS; END Behavior;

Practice 3： 4 -bit shift register --(shift 4. vhd) LIBRARY ieee; USE ieee. std_logic_1164. all; ENTITY shift 4 IS PORT( R : IN STD_LOGIC_VECTOR(3 DOWNTO 0); Clock, L, w : IN STD_LOGIC; Q : BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0)); END shift 4; ARCHITECTURE Behavior OF shift 4 IS BEGIN PROCESS BEGIN WAIT UNTIL Clock'EVENT AND Clock='1'; IF L='1' THEN Q<=R; ELSE Q(0)<=Q(1); Q(1)<=Q(2); Q(2)<=Q(3); Q(3)<=w; END IF; END PROCESS; END Behavior;

Practice 4：Marquee LIBRARY ieee; USE ieee. std_logic_1164. all; USE IEEE. STD_LOGIC_UNSIGNED. ALL; ENTITY ring IS PORT( Reset, Clock : IN STD_LOGIC; Q : BUFFER STD_LOGIC_VECTOR(1 TO 8)); END ring; ARCHITECTURE Behavior OF ring IS signal clk_reg: STD_LOGIC_VECTOR(22 DOWNTO 0); signal hhh: STD_LOGIC; BEGIN PROCESS(Clock) -- Frequency division, original clock is 50 MHz => 20 ns / cycle BEGIN IF Clock’EVENT AND Clock=’ 1’ THEN clk_reg <= clk_reg + ‘ 1’; END IF; END PROCESS; hhh <= clk_reg (22); -- New clock after frequency division, 50 MHz/2 23 => 0. 16 s / cycle

Practice 4：Marquee (continued) PROCESS (Reset, hhh) -- hhh is the clock after frequency division BEGIN IF Reset=’ 1’ THEN Q <= (OTHERS => ‘ 0’); ELSIF hhh’EVENT AND hhh=’ 1’ THEN FOR i IN 8 DOWNTO 2 LOOP Q(i) <= Q(i-1); END LOOP; Q(1) <= NOT Q(8); END IF; END PROCESS; END Behavior;